Pioneer VSX-56TXi Service Manual page 163

5
No. Pin Name I/O
25 TPB0_N I/O
33 TPB1_N I/O
39 TPB2_N I/O
26 TPB0_P I/O
34 TPB1_P I/O
40 TPB2_P I/O
31 TPBIAS0 I/O
38 TPBIAS1 I/O
44 TPBIAS2 I/O
−
46 R1
−
47 R0
49 FILTER0 I/O
50 FILTER1 I/O
−
52 XI
−
53 XO
22 CPS I
19 MSPCTL I
61 LINKON O
High Speed Data Interface (HSDI) Port 0 Pins
No. Pin Name I/O
136 HSDI0_60958_IN I
HSDI0_AMCLK_
137 I
IN
140 HSDI0_AVz O
138 HSDI0_CLKz I
143 HSDI0_D0 I/O
144 HSDI0_D1 I/O
147 HSDI0_D2 I/O
148 HSDI0_D3 I/O
149 HSDI0_D4 I/O
150 HSDI0_D5 I/O
151 HSDI0_D6 I/O
152 HSDI0_D7 I/O
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Twisted pair B differential signal terminals.
For an unused port, TPBN and TPBP signals are left open (i.e., TSB43CA42 for Port 2).
Twisted pair bias output. These signals provide the 1.86-V nominal bias voltage needed for proper
operation of the twisted pair driver and receivers for signaling an active connection to a remote node.
For an unused port, TPBIAS is left unconnected (i.e., TSB43CA42 for Port 2).
Current setting resistors. These pins are connected to external resistors to set the internal operating
currents and cable driver output currents.
PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter
required for stable operation of the internal frequency-multiplier PLL, which is using the crystal oscillator.
Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental mode
crystal.
Cable power status. This input to iceLynx-Micro detects if cable power is present. This pin must be
connected to the cable power through 390-kΩ resistor.
Maximum speed of PHY. When this signal is high; S100 and S200 operation.
When this signal is low; S100, S200, and S400 operation.
Link-on output. This signal is asserted whenever LPS is low and a link-on packet is received from the 1394
bus.
60958 data input
Audio master clock input. This clock is used to decode the biphase encoding of 60958 data. This pin is
also used to input the 1.5*BCLK for flow control mode.
HSDI port 0 available. Programmable. Default active low. For receive from 1394, this signal indicates if a
1394 packet is available in the receive buffer for reading. The HSDI_AV signal for MPEG2 data also
depends on time stamp based release.
For transmit to 1394 , this signal indicates buffer level in HSDI TX modes 8 and 9 by programming a CFR.
If the buffer level is above a programmed level, HSDI_AV will be asserted.
HSDI port 0 clock. Programmable. Default rising edge sample. This clock is used to operate the HSDI port
0 logic. In parallel mode, the maximum clock is 27 MHz. In serial mode, the maximum clock is 70 MHz.
This signal is output to HSDI1_CLKz in pass-through mode.
This signal is used as HSDI0_MLPCM_BCLK for DVD-audio transmit.
HSDI port 0 data 0 pin. Data 0 is the least significant bit on the HSDI data bus. In serial mode, only
HSDI0_D0 is used. This signal is output to HSDI1_D0 in pass-through mode.
This signal is used as HSDI0_MLPCM_D0 for DVD-audio transmit.
HSDI port 0 Data 1 pin This signal is output to HSDI1_D1 in pass-through mode.
This signal is used as HSDI0_MLPCM_D1 for DVD-audio transmit.
HSDI port 0 Data 2 pin This signal is output to HSDI1_D2 in pass-through mode.
This signal is used as HSDI0_MLPCM_D2 for DVD-audio transmit.
HSDI port 0 Data 3 pin This signal is output to HSDI1_D3 in pass-through mode.
This signal is used as HSDI0_MLPCM_A for DVD-audio transmit.
HSDI port 0 data 4 pin This signal is output to HSDI1_D4 in pass-through mode
HSDI port 0 data 5 pin This signal is output to HSDI1_D5 in pass-through mode
HSDI port 0 data 6 pin This signal is output to HSDI1_D6 in pass-through mode
HSDI port 0 data 7 pin Data 0 is the most significant bit on the HSDI data bus.
This signal is output to HSDI1_D7 in pass-through mode
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Pin Function
Pin Function
VSX-56TXi
7
8
A
B
C
D
E
F
163
8