Pioneer VSX-56TXi Service Manual page 160

1
Pin Function
Miscellaneous Pins
No. Pin Name
A
64 DISABLE_IFn
62 HPS
63 LOW_PWR_RDY
88 WTCH_DG_TMRn
B
60 RESET_ARMn
59 RESETn
Power and Ground Pins
No. Pin Name
1,21,55,76,
102,117,131, VSS
146,162,176
24,27,35,45 AGND
C
54 PLL_GND
4,20,56,75,
101,116,130, VDD
145,161,175
23,28,32,41,48 AVDD
51 PLL_VDD
Regulator Pins
No. Pin Name
D
73 REG_ENn
74 REG_OUT0
115 REG_OUT1
160 REG_OUT2
External CPU Interface Pins
No. Pin Name
E
95 MCIF_ACKz
120 MCIF_ADDR1
F
160
1
2
I/O
Interface disable. When asserted, the interfaces are put into a high-Z state. Interfaces include: ex-CPU,
I
HSDI, GPIO, and WTCH_DG_TMRn.
Host power status. This indicates the power status of the external system to iceLynx-Micro. A rising edge
I indicates the system CPU has been turned ON. (The internal ARM must wake up.) A falling edge
indicates the system CPU has been turned OFF. (The internal ARM decides if power down is
necessary.)
Output to system to indicate iceLynx-Micro is ready to go into a low power state. The ARM and
O
WTCH_DG_TMRn control this pin.
Watch dog timer (for the ARM). iceLynx-Micro hardware asserts this pin whenever ARM software has
O
not updated the Timer2 register within the allowed time period.
I ARM reset. This signal resets the internal ARM processor.
Device reset. This signal resets all logic.This includes the PHY,link core, memory, the ARM, and random
I
logic.
I/O
−
Digital ground
−
Analog ground
−
PLL ground
−
Digital power supply. Must be set to 3.3-V nominal.
−
Analog power supply. Must be set to 3.3-V nominal.
−
PLL power supply. Must be set to 3.3-V nominal.
I/O
Internal regulator enable. The iceLynx-Micro core voltage is 1.8 V. Internal regulators are used to
I
regulate the 3.3-V VDD inputs to 1.8 V. This pin enables the regulators.
O 1.8-V regulator output. This pin must be connected to ground using a 0.1-µF capacitor.
O 1.8-V regulator output. This pin must be connected to ground using a 0.1-µF capacitor.
O 1.8-V regulator output. This pin must be connected to ground using a 0.1-µF capacitor.
I/O
MCIF acknowledge pin. Default active low. iceLynx-Micro asserts this signal if it has completed the MCIF
request. This signal is driven when chip select (CS) is asserted. This signal is used for the following
I/O modes:
• 68000 + wait I/O access
• I/O Type-3 MPC850
MCIF address 1 pin. This data pin is the least significant bit of the MCIF address bus.
I MCIF_ADDR0 is internally grounded. Only 16-bit addressing is allowed. MCIF_ADDR1 must be
connected to the Address1 signal of the system CPU.
VSX-56TXi
2
3
Pin Function
Pin Function
Pin Function
Pin Function
3
4
4