Sony STR-DA9000ES Service Manual page 127

• DIGITAL BOARD IC2251 CXD9782R (DSP2)
Pin No. Pin Name
1 VDDI
EXTIN
2
WMD1, WMD0
3, 4
5 MOD1
MOD0
6
7 VSS
8 XRST
VSS
9
SCKOUT
10
11 VDDI (PLL)
SYNC
12
PAGE2 to PAGE0
13 to 15
16 PLOCK
17 BTACK
VDDE
18
VSS
19
D31 to D29
20 to 22
23 A17
VSS
24
SDO3, SDO4
25, 26
SDI1, SDI2
27, 28
29 LRCKI1
VSS
30
D28, D27
31, 32
A16
33
34 A15
SDI3
35
L2
36
VDDI
37
38 BCKI1
SDI4
39
MS
40
A14, A13
41, 42
43, 44 D26, D25
VSS
45
BCKI2
46
FS2, FS1
47, 48
49 SPDIF
A12
50
D24 to D22
51 to 53
VDDE
54
55 VSS
I/O
— Power supply terminal (+2.6V)
I
Master clock signal input terminal Not used
I
External memory wait mode setting terminal Fixed at "H" in this set
Operation mode setting terminal "L": enhanced mode, "H": normal mode
I
Fixed at "H" in this set
Operation mode setting terminal "L": single chip mode, "H": can not use
I
Fixed at "L" in this set
— Ground terminal
I
System reset signal input from the main system controller "L": reset
—
Ground terminal
O
Internal serial clock signal output terminal Not used
— Power supply terminal (+2.6V) (for PLL)
I
Sync/non-sync setting terminal "L": sync, "H": non-sync Fixed at "H" in this set
O
External memory page selection signal output terminal Not used
O
Internal PLL lock signal output terminal Not used
O Boot mode state display signal output terminal Not used
—
Power supply terminal (+3.3V)
—
Ground terminal
I/O
Two-way data bus with the S-RAM
O Address signal output terminal Not used
—
Ground terminal
O
Audio serial data output to the DC cut digital filter
I
Audio serial data input from the DSP1
I L/R sampling clock signal (44.1 kHz) input from the DSP
—
Ground terminal
I/O
Two-way data bus with the S-RAM
O
Address signal output terminal Not used
O Address signal output to the S-RAM
I
Audio serial date input from the DSP
—
Not used
—
Power supply terminal (+2.6V)
I Bit clock signal (2.8224 MHz) input from the DSP
I
Audio serial data input from the DSP
Master/slave setting terminal "L": internal clock, "H": external clock
I
Fixed at "L" in this set
O
Address signal output to the S-RAM
I/O Two-way data bus with the S-RAM
—
Ground terminal
I
Bit clock signal (2.8224 MHz) input terminal Not used
I
Sampling frequency selection signal input terminal Not used
I SPDIF signal input terminal Not used
O
Address signal output to the S-RAM
I/O
Two-way data bus with the S-RAM
—
Power supply terminal (+3.3V)
— Ground terminal
Description
STR-DA9000ES
127