Sram; And Gate - JVC RX-5030VBK Service Manual

RX-5030VBK
4.12 LP61L1024S-12-X (IC641) : SRAM
• Pin layout
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
4.13 TC74HC08AF-X(IC611) : AND gate
• Block diagram
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
1-20 (No.22025)
1 V
32
DD
2 A15
31
3 CS2
30
4 WE
29
5 A13
28
6 A8
27
7 26 A9
8 25 A11
9 24 OE
10 23 A10
11 22 CS1
12 I/O8
21
13 I/O7
20
14 I/O6
19
15 I/O5
18
16 I/O4
17
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
(TOP VIEW)
• Block diagram
V
DD
Vss
A0
DECODER
A16
CS2
CS1
CONTROL
OE
WE
• Pin function
SYMBOL DESCRIPTION
A0 - A16 Address Input
I/O1 - I/O8 Data Input/Output
CS1, CS2 Chip Select Inputs
WE Write Enable Input
OE Output Enable Input
VDD Power Supply
Vss Ground
NC No Connection
• Truth table
A B Y
L L L
L H L
H L L
H H H
CORE
ARRAY
I/O1
DATA I/O
I/O8