Main(Sub Cpu) Schematic Diagram - JVC GZ-MG40US Schematic Diagrams

MAIN(SUB CPU) SCHEMATIC DIAGRAM

0 1 MAIN(SUB CPU)
L1001
NQR0129-002x
TO MAIN IF LIT_3V
(CN101)
REG_3.1V
L1002
TO MAIN IF AL_3.1V
10u T
(CN103,110) C1004
0.1 C1005
R1001
10/6.3
100k
GND
R1063 47k
TO MAIN IF(CN103)
R1064 1k DBATT
D_BATT
V_BATT 2 1
V_BATT
T_BATT
T_BATT
I_MTR
C1025
I_MTR IC1003
0.1
DC_CHEK
DC_CHEK
ADP_L
ADP_L
3 4
TO MAIN IF(CN103)
CHRG_EVR
CHRG_EVR
REG_CS
REG_CS
CLK_OUT
2.2K
TO MAIN IF(CN103)
UNREGCHK
UNREGCHK
SBD5
SBD5
SBT5
SBT5
TO MAIN IF
ZGH_THRU
(CN110)
ZGH_THRU
ZGH_OUT
ZGH_OUT
TO MAIN IF
(CN101,CN103,CN110)
SJIG_RST
SJIG_RX
SJIG_TX
TO MAIN IF
(CN110)
WORD
R1016
2.2k
TO MAIN IF(CN103)
DATA_OUT
TO MAIN IF(CN101),
AUDIO,V I/O
ANA_CLK
ANA_CLK
ANA_OUT
ANA_OUT
LCD_CS
LCD_CS
TO MAIN IF
(CN101) LCD_CTL
LCD_CTL
TO MAIN IF(CN101),
AUDIO,V I/O
ANA_CLK
ANA_CLK
ANA_OUT
ANA_OUT
AUDIO_CS
AUDIO_CS
L_MUTE
L_MUTE
A_MUTE
A_MUTE
TO AUDIO
PD_L
PD_L
BUZZER
TO MAIN IF
CHRG_LED
Q1003
(CN101) R1009 DTA124EE-X
680
CHRGLED R1056
4.7k
TO MAIN IF(IC121)
3AAZEROG
3AAZEROG
PS_ZEROG
PS_ZEROG
TO MAIN IF(CN101)
R1017 1k MONI_SW
LCD_OPEN
LCDRVS
R1018 1k
LCD_RVS
R1020 1K ACESLED
ACES_LED
R1022 1k DIAL_PB
PLAY_SW
DIAL_OFF
R1023 1k
POFF_SW
R1024 1k DIAL_REC
REC_SW
R1025 PMEDIA
1k
P_MEDIA
R1019 1k SETSW
SET_SW
TO MAIN IF(CN104)
R1028 1k ZOOMSW
TO MAIN IF ZOOM_SW
R1029 1k KEY_ACH
(CN101) KEY_A
TO MAIN IF R1030 1k KEY_BCH
KEY_B
(CN103)
R1031 1k KEY_CCH
KEY_C
TO MAIN IF
INFOSW
R1008 1K
(CN101) INFO_SW
TO MAIN IF(RMC)
IR_RMC
IR_RMC
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
IC1002
RS5C314-X
CS VDD
NAX0564-001X
CLK XIN X1002
SIO XOUT
C1006
VSS INTR
8p
D1002
R1007
1SS376-X
4.7k
72
ANA_CLK
70
55
R1014 56
OPEN R1006
EEPRM_CS
IC1004
4.7k 97 EEP_CS
SCPU_SO
SN74AHC1G08DC-X
51 SCPU_IN
D1003 74AHC1G08GW-X SCPU_SI
Q1004 OPEN 52 SCPU_OUT
2SC5658/ SCPU_SCK
50 SCPU_CLK
QRS/-X
68 DATA_IN
69 DATA_OUT
67 CLK_OUT
SCPU_CS
79 SCPU_CS
22 VDD
C1044
0.01
28 RTC_CS
REG_CS
1 REG_CS
OSD_CS
39 OSD_CS
EEPRM_DI
IC1005
14 EEP_IN
SN74AHC1G04DC-X EEPRM_DO
15 EEP_OUT
74AHC1G04GW-X
EEPRM_CK
13 EEP_CLK
ANA_CS
D1001 9 ANA_CS
R1051
R1053 DA221-X
150k 2.7k 93 BZ_FREQ
3
Q1002
94 BZ_ENV
2SC4617/QR/-X 2
1
R1052
18k ANA_RST
90 ANA_RST
R1055
TG2_RST
10k
10 SYTG_RST
R1054 C1031
47k 1
Q1001
DTC124EE-X
LCD_CS
2 LCD_CS
17 VDD
C1046
0.1
LCDRVS
6 LCD_RVS
PSCTL
84 PS_CTL
(No.YF109)2-7
5 4
1 2 3
R1077
1M
71 27 49 95 88 74 73 92 25 100 99 98 18 37 11 8 7 59 57 61 66 34
ANA_CLK
RXD
TXD
IC1001
MN102H60GJA
91 89 31 32 30 5 35 42 12 82 19 20 21 24 23 40 86 87 85 4 41 3
3 2 1
X1001
NAX0784-001X
2-8(No.YF109)
R1046
OPEN
S 3
G
2
D 1 Q1005
2SJ347-X
43 54
I_MTR
I_MTR 45
KEY_CCH
KEY_C 46
KEY_BCH
KEY_B 64
KEY_ACH
KEY_A 63
ZOOMSW
ZOOM_SW 47
UNREGCHK
UNREGCHK
62
T_BATT
T_BATT 44
R1065
1k
V_BATT
V_BATT 65
R1043
100k
RTC_INT 96
TVSEL
NT_PAL 48
AFE_RST 16
DSP_RST 29
ZEROG_H
ZEROG_H 26
CHRGLED
CHRGLED 81
ACESLED
ACESLED 60
IR_RMC
REMOTE 58
C1001
0.1
VDD 83
R1086
3AAZEROG 53
0R0
3AAZEROG OSD_CS
ZEROZINT 77
OSD_VD 78
R1066 1k ADP_L
ADP_L 36
BATT_H
BATT_H 80
MONI_SW
LCD_OPEN 33
INFOSW
INFO_SW 38
JLIP_INT 76
NMI 75
R1037 TO MAIN IF(CN101)
1k
PDET
P_DET
R1045
SDET 1k
S_DET
TO P.PRCS
SYSSEL0
SYSSEL0
SYSSEL1
SYSSEL1
TVSEL
R1068 TVSEL
SCPU_CS
100k
SCPU_CS
SCPU_SCK
SCPU_SCK
SCPU_SO
SCPU_SO
SCPU_SI
SCPU_SI
EEPRM_CS
EEPRM_CS
EEPRM_CK
EEPRM_CK
EEPRM_DO
EEPRM_DO
EEPRM_DI
EEPRM_DI
AFE_RST
R1071
100k
V27_OUT
V27_OUT
TO TG133
TG2_RST
TG2_RST
TO DSP MEM
FLSH_RST
FLSH_RST
TO DSP
ZEROG_H
TO V I/O,DSP
DSP_RST
TO V I/O
OSD_CS
OSD_VD
TO V I/O
ANA_RST
ANA_RST
ANA_CS
ANA_CS
TO MAIN IF
ANA_CLK
(CN101),
ANA_CLK
ANA_OUT V I/O,
ANA_OUT
AUDIO
ANA_IN
ANA_IN
PSCTL TO V I/O
PSCTL
y10563001a_rev0.1