JVC GZ-MG40US Schematic Diagrams page 14

MAIN(TG133) SCHEMATIC DIAGRAM
0 1 MAIN(TG133)
TO CCD(CN5001)
CN105
QGF0547C2-24X
REG_+15V 1
REG_+15V 2
REG_-7.5V 3
REG_-7.5V 4
CCD_CTL 5
R5514
GND
10
GND
GND
CCD_OUT
GND
GND
GND
RG 13
H1 14
H2 15
SUB 16
R5515
10
V1 17
R5516
10
V2 18
R5517
10
V3 19
R5518
10
V4 20
GND 21
G_RST 22
REG_3.1V 23
P_GYAMP 24
TO P.PRCS P_GYAMP
REG_3.1V
TO GYRO,
G_RST
P.PRCS
GND
TO DSP
CCD_CTL
TG_CS
CAM_CLK
TO OP DRV,
CDS,P.PRCS
CAM_OUT
TO SUB CPU
TG2_RST
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
36 35 34 33 32 31
37 VDD3
38 SGMOD
39 VM
40 V2
41 V4
IC5501
42 V1
CXD3602AR
43 VH
TG/V-DRIVER
C5514
44 V3
1/35
C5511
45 SUB
T 0.1
D5501
46 VL
1SS355-X
47 DSGAT
R5511
48 VDD4
100k
1 2 3 4 5 6
L5507
NQR0129-002X
C5502 C5501
0.1 0.1
(No.YF109)2-25
NAX0674-001X
X5501
(72MHz_CXO)
C5508
0.1
GND
OUT
CTL
VDD
30 29 28 27 26 25
C5507
0.1
VDD2 24
NC 23
TEST2 22
XPBLK 21
R5510
0
XCLPDM 20
GND(CDS) 19
R5508 10
XSHD 18
R5507 10
XSHP 17
C5504
AVD(CDS) 16
0.1
XCLPOB 15
R5509
AVD(H) 14 0
H2 13
R5506
10
7 8 9 10 11 12
R5519
IC5502
MM3143DN-X
(3.3V_REG)
C5518
0.1
2-26(No.YF109)
TL5501
L5503 NQR0129-002X
C5505
C5506
10/6.3
T
R5513
C5526
C5523
1
1
C5522 C5525
R5512
0.01 0.01
0Ω
5 4
5 4
1 2 3
1 2 3
C5521
C5524
1
1
L5501
10µ
L5502 NQR0129-002X
C5519 C5520
47/4 0.1
T
y30329001a_rev0.1
TO P.PRCS
TG_ID
TG_VD
TG_HD
MCLKI
TO CDS
OBCLP
PBLK
ADCLK
TO CDS
CDS_3V
SHD
SHP
REG_4.8V
CAM_3.1V
GND
TO MAIN IF,
REG+CCD
V I/O
TO MAIN
REG-CCD
(CN103)