Sony STR-DA3100ES Service Manual page 81

Pin No. Pin Name
63 LRCKO
64 BCKO
65 VDDI
66 VSS
67, 68 D18, D17
69, 70 A10, A9
71 CAS
72 RAS
73 VDDI
74 HDIN
75 HCLK
76 HCS
77, 78 A8, A7
79, 80 D16, D15
81 VSS
82 HDOUT
83 HACN
84 CS0
85 WE0
86 A6
87 to 89 D14 to D12
90 VDDE
91 VSS
92 to 94 D11 to D9
95 A5
96 VDDI
97 TCK
98 TDI
99 TDO
100 TMS
101 XTRST
102 VSS
103, 104 D8, D7
105, 106 A4, A3
107, 108 GP10, GP9
109 VDDI
110 GP8
111 GP7
112 GP6
113, 114 A2, A1
115, 116 D6, D5
117 VSS
118, 119 GP5, GP4
120 GP3
121 NC
122 A0
123 to 125 D4 to D2
126 VDDE
127 VSS
128, 129 D1, D0
I/O
O L/R sampling clock signal (44.1 kHz) output to the lip sync adjust
O Bit clock signal (2.8224 MHz) output to the lip sync adjust
– Power supply terminal (+2.6V)
– Ground terminal
I/O Two-way data bus with the S-RAM
O Address signal output to the S-RAM
O Column address strobe signal output terminal Not used
O Row address strobe signal output terminal Not used
– Power supply terminal (+2.6V)
I Serial data input from the main system controller
I Serial data transfer clock signal input from the main system controller
I Chip select signal input from the main system controller
O Address signal output to the S-RAM
I/O Two-way data bus with the S-RAM
– Ground terminal
O Serial data output to the main system controller
O Acknowledge signal output to the main system controller
O Chip select signal output to the S-RAM
O Write enable signal output to the S-RAM
O Address signal output to the S-RAM
I/O Two-way data bus with the S-RAM
– Power supply terminal (+3.3V)
– Ground terminal
I/O Two-way data bus with the S-RAM
O Address signal output to the S-RAM
– Power supply terminal (+2.6V)
I Simplicity emulation clock signal input terminal Not used
I Simplicity emulation data input terminal Not used
O Simplicity emulation data output terminal Not used
I Simplicity emulation data input start and end select Not used
I Simplicity emulation non-sync break signal input terminal Not used
– Ground terminal
I/O Two-way data bus with the S-RAM
O Address signal output to the S-RAM
O Not used
– Power supply terminal (+2.6V)
O Not used
I L/R sampling clock signal (44.1 kHz) input terminal
O Not used
O Address signal output to the S-RAM
I/O Two-way data bus with the S-RAM
– Ground terminal
O Not used
O Error signal output to the main system controller
– Not used
O Address signal output terminal Not used
I/O Two-way data bus with the S-RAM
– Power supply terminal (+3.3V)
– Ground terminal
I/O Two-way data bus with the S-RAM
STR-DA3100ES
Description
81