Sony STR-DA3100ES Service Manual page 78

STR-DA3100ES
• IC Pin Function Description
DIGITAL BOARD IC2201 CXD9718Q (DSP1)
Pin No. Pin Name
1 VSS
2 XRST
3 EXTIN
4 FS2
5 VDDI
6 FS1
7 PLOCK
8 VSS
9 MCLK1
10 VDDI
11 VSS
12 MCLK2
13 MS
14 SCKOUT
15 LRCKI1
16 VDDE
17 BCKI1
18 SDI1
19 LRCKO
20 BCKO
21 VSS
22 KFSIO
23 to 26 SDO1 to SDO4
27 SPDIF
28 LRCKI2
29 BCKI2
30 SDI2
31 VSS
32 HACN
33 HDIN
34 HCLK
35 HDOUT
36 HCS
37 SDCLK
38 CLKEN
39 RAS
40 VDDI
41 VSS
42 CAS
43 DQM/OE0
44 CS0
45 WE0
46 VDDE
47 WMD1
48 VSS
49 WMD0
50 PAGE2
78
I/O
– Ground terminal
I System reset signal input from the main system controller "L": reset
I Master clock signal input terminal Not used
I Sampling frequency selection signal input terminal Not used
– Power supply terminal (+2.6V)
I Sampling frequency selection signal input terminal Not used
O Internal PLL lock signal output terminal Not used
– Ground terminal
I System clock input terminal (13.5 MHz)
– Power supply terminal (+2.6V)
– Ground terminal
O System clock output terminal (13.5 MHz)
Master/slave setting terminal "L": internal clock, "H": external clock
I
Fixed at "L" in this set
O Internal system clock output terminal Not used
I L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver
– Power supply terminal (+3.3V)
I Bit clock signal (2.8224 MHz) input from the digital audio interface receiver
I Audio serial data input from the A/D converter
O L/R sampling clock signal (44.1 kHz) output to the DSP2
O Bit clock signal (2.8224 MHz) output to the DSP2
– Ground terminal
I Audio clock signal input terminal
O Audio serial data output to the DSP2
O SPDIF signal output terminal Not used
I L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver
I Bit clock signal (2.8224 MHz) input from the digital audio interface receiver
I Audio serial data input from the digital audio interface receiver
– Ground terminal
O Acknowledge signal output to the main system controller
I Serial data input from the main system controller
I Serial data transfer clock signal input from the main system controller
O Serial data output to the main system controller
I Chip select input from the main system controller
I Write signal input terminal Not used
O SD-RAM chip enable output terminal Not used
O Row address strobe signal output terminal Not used
– Power supply terminal (+2.6V)
– Ground terminal
O Column address strobe signal output terminal Not used
O Output terminal of data input/output mask Not used
O Chip select signal output to the S-RAM
O Write enable signal output to the S-RAM
– Power supply terminal (+3.3V)
I External memory wait mode setting terminal Fixed at "H" in this set
– Ground terminal
I External memory wait mode setting terminal Fixed at "H" in this set
O External memory page selection signal output terminal Not used
Description