Radio Shack TRS-80 Service Manual page 51

WAIT STATE GENERATION ANDWAITIMOUT lOGIC
As previously mentioned, a wait stale to the CPU can be
initiated by an output to the Drive Select lalch with 06 set.
Pin 5 of U18 will go high after tnis operation. This signal is
inverted by 1/6 of U1 and is routed to the CPU board where
it forces the Z-aO into
a
wilit state. The Z.sO will remain in
the wait $late as long as WAIT" is low. Once initiated, the
wail state will remain until one of four conditions arc satis·
fied. One half of UIO (a fille input NOR gate) is used to per-
form this function. INTRa, ORa, RESET, andWAITIMOUT
are the inputs to the NOR gate. If anyone of these inputs are
active (logic high). the output of the NOR gate (U10 pin 6)
will go low. This output is tied to tne clear input of the wait
latch. This ~!1"1l1, when low, will clear the a output (Ula
pin 5) and set tnc a" output (U1S pin 6). This condition
causes WAIT" to go high and allows the Z-80 to exit the wait
stale_ U20 is a 12-bit binary counter which serves as a watch-
dog timer to insure that
iI
wait condition will not persist
long enough to destroy dynamic RAM wntents. The counter
is clocked by a lMHz signal and is enabled to count when its
reset pin is low (U20 pin 11). A logic high on U20 pin 11
resets the counter ouputs. U20 pin 15 is the dillide by 1024
output and is user! to generate the signal WAITIMOUT.
This watchdog timer logic will limit the duratiun of a wait to
1024,uscc. ellen if thc FDC chip hils to generate a data
reQuest or an interrupt request.
CLOCK GENERATION lOGIC
A 4MHz crystal oscillator and a divide by 2 and divide by 4
counter generate the clock signals required by the FDC
board. The basic 4MHz oscillator is implemented with two
invertors (1/3 of U251 and a Quartz crystal (Yl). One half of
U24 is used to divKMt the basic 4MHz clcx:k by 2 to produce
a 2MHz output at U24 pin 6. This output is again divided by
2 using the remaining half of U24 to produce a lMHz output
at U24 pin a. The 1MHz clock is used to drive the clock
input of the 1793 FDC chip and the clock input of the
watchdog time (U20).
DISK BUSSELECTOR LOGIC
As mentioned pfllviously, the Model III Floppy Disk BOilrd
supports up to four drives (two internal, two external). This
function is implemented by using
two
disk drive interlace
buses, one for the internal drives and one for the external
drives. J4 is the edge connector used for the internal drives
and Jl is tIM! edge connector for the external drives. U22
la quad 2 to 1 data selector) is used to select which set
of Inputs from the disk drive buses are routed
\'I)
the
1793
FDC chip. U22 pin 1 is the control pin for the data selector.
If U22 pin 1 is low. the external inputs arc selected, other·
wise the internal inputs are selected. This control signal
(labeled EXTSEl"l is derived from the outputs of the Drive
Select latch_ If Drive 2 or Drive 3 is selected. U17 pin 1
44
will go low indicating that an external drive is selected.
One half of U10 (a five input NOR gatel is used to detect
when any of the four drives are selected. The output of this
NOR gate IUl0 pin 5) is inverted and is used as the head load
timing and ready signal for the 1793 FOC chip. Therefore if
any drive is selected, the hBiid is aswmed to be loaded and
the selected drive is assumed to be ready.
READM'RITE DATA PULSE SHAPING lOGIC
Two one--shots
(112
of U15 and 1/2 of U23) are used to
insure that the read and write data PlJlses are approximately
450nsec in dlSation.
DISK BUS OUTPUT DRIVERS
High current open collector drivers (U21. U9, and Ull are
used to buffer the output signals from the Drive Select
latch and the FDC chip to the floppy disk drives. Note from
the schematic that each output sign;)1 to the driv8S has
two buffers associated with each signal, one set is used for
the internal drive bus and the other set is used for the ex·
ternal bus. No select logic is reQuire<! for these output sig·
nals since the drive select bits define which drive is active.
WRITE PRECOMPENSATION AND CLOCK RECOVERY
lOGIC
The Write Precompensation and Read Clock Recovery logic
is comj:Kised of Ul1 (WD16911, U13 (WD2143) and UI4
(lSS29l, along with a few passive components. The W01691
is an lSI device which minimizes the elltemallogic required
to interface the 1793 FOC chip to a disk drive. With the use
of an external VCO, U14, the W01691 will derive the RClK
signal for the 1793, while providing an adjustment signal for
the VCO, to keep the RCLK synchronous with the read data
from the drive. Write precompensation control signals are
also provided by the WDl691 to interface directly to the
WD2143 (U13) clock generator. The Read Clock Recovery
section of tnc W01691 has five inputs: OOEN", VCO,
ROD", WG. and VFOe"/WF. It also hu three Outputs:
PU, PO", and RClK. The inputs VFOE"!WF and WG when
both are low. enable the Clock Recovery logic. When WG is
high, a write operation is in progress and the Clock Recovery
circuits are disOOrcd regardless of the state of any other
input$.
The Write Precompensation section of the WOl691 was
designed to be used with the W02143 clock generator.
Write Precompensation is not used in single density mode
and the signal DOEN" when high indicates this condition.
In double density mode (DOEN" '" 01, the signals EARLY
and lATE are used to select a phase input (01 - 04) on the
leading edge of WOIN. The STB line is latched high when
this occurs, causing the W02143 to start its pulse generation.