Radio Shack TRS-80 Service Manual page 23

VIDEO
The Video ~ction can be subdivided into four parts;
A. Vidco RAM wilh associaled addressing and data buffer
B. Molin oscillator and divider chain
C. Character generation logic
D. Wait logic
A. The video RAM consists of two 2114 static RAMs (UB 1.
U82) which gives 1024 II K) bytes of RAM. Addressing
from the divider chain or the Z-80 CPU comes from the
LS1S1 multiplexors (U69, U70, U71). The video data is
buffered to the CPU data bus through an LS245 (U6]!.
or to the character generator logic by Ihe LS273 latch
U6B. Addressing control is determined by the $ignal
RSVID' which IS described in paragraph O.
B. The main oscillator consists of inverters from U2, cryslal
YI, and discretes Rl, R5. andCl. TheoscillalOf runs in
the fundamental mode at a frequency of 10.1376 MHz.
This basic frequency is divided by two in U3 and be·
comes CLOCKI2. The CLOCK and CLOCK/2 signals are
fed to mux U4 which provides Ihe divide' chain with the
CHAIN signal 1633.6 kHz) provides the shift register
U52 with the SHIFT signal, and i1lso supplies the signal
LATCH 1118 Ihe rate of SHIFT! to various
p<!rts.
MOD·
SE L selects either the 64 character or 32 character mode.
(Refer to the Video Timing diagram.) The main divider
chain consists of two LS393s (U20. US6) and one LS14
(U 1). This divider chain, connected as one long ripple
counter, presents the character COUnl, Ihe line and row
counl. and the horizontal and vertical drive signals to
the rest of the video section. The horizontal drive signal
(HDRVj runs at 15.840 kHz and resulTs in 80 char·
acters per line; 64 displayed and 16 blanked. The line
count IL 1 to LSI runs modulo 12 (i.e., twelve horizontal
lines per character block!. The row counter (Rl to RS
and VDRV) runs modulo 22 (60 Hz). or modulo 26
150 Hzl depending which jumper oPtion, "An. or nBw
or "C", has been selected.
C. The character generation logic consins of a latch (LS273·
U6S) to hold the ASCII data, a ROM which comains the
dol patTern making up the characters, a shift register
{LS166 . US21 which serializes the S·bit data 10f display
on the sa-ellO. and the associaled limtng and control
signals provided by the divider chain and oscillato. cit-
cuits. On the rising edge of LATCH the lS273 stores the
ASCII byte f.om Ihe video RAMs. This data is presented
to the character gl!Oera;:or ROM to form pari olthe ad-
dress of the character to be displayed. The other addres-
sing informaTion comes from the diVider chain ell to
L4) to select the scan line or the character to bedisplayed.
(There are lwelve scan lines in each character block.) On
Ihe next LATCH pulse the data from the ROM is latched
Into the shih register and shihed out bv the SHIFT
clock. The SHIFT clock runs eighl time-> fasler than
LATCH, hence there are eight horllontal dots per char·
acter line The LATCH signal into the shift register is
qualified by OLYBLANK so that during horizontal reo
trace, vertical retrace, ilnd the last four scan lines of each
elliulleter displayed, the shift register will shift out zeros.
«...
nfI.r
"':UlIU UlIU1Jl1Ulr..J1IL'lJUlf
" ... , JlJL..r1Jl..- 'lJ'"1...n..J'"J""'JL
... DGI ,
..n....r
J l...
r t
J1.J'"""' t ...r...Jl.... 'L.J"L
......
,.~
....
' _
..
_
....
-
"."'''''''''-~'''-'
FIGURE 2. VIDEO TIMING DIAGRAM
16