Radio Shack TRS-80 Service Manual page 50

TECHNICAL DESCRIPTION
DRIVE SELECT LATCH AND MOTOR ON LOGIC
-Only one of these bits should be set per output.
$electing a drive prior to a disk I/O operation is accom-
plished by doing an OUT instruction to port F4H with the
proper bit set. The following table describes the bit alloca-
tion of the Drive Select Latch.
bit 7 is set, an NMI will be generated by an FDC interrupt
request. If data bit 7 is reset, interrupt rCQuests from the
FOC <He disabled. If data bit 6 is set, an NMI wilt be gener-
ated by Motor Time Out.
If
data bit 6 is reset, interrupts on
Motor Time Oul are disabled. An IN instruction from
port
E4H enables the CPU to question the Floppy Disk Con-
troller Board to determine the wurce of the non-maskable
interrupt. Data bit 7 indicates the status of FDC interrupt
request (0
=
true, 1 ,. falsel. Data bit 6 indicates the status of
Motor Time Out (0" true, 1 • false). Data bil 5 indicates the
status of the front panel reset (0 ., true, 1
=
false). The con-
trol signal ADNMIMA$KREG- when active (logic 0), gates
this SUItus onto the CPU data bus.
FUNCTION
Selects Drive 0 when set -
Selects Drive 1 whcn set •
Selects Drive 2 when set -
Selects Drive 3 when set -
Side 0 selected when reset,
Side 1 selected if set
Write Preoom. engaged .....hen sel,
disabled if reset
Generate waits if set,
no weits if reset
Selects MFM mode if set,
FM mode if reset
05
07
06
00
01
02
03
04
DATA BIT
A hex "D" flip·flop (U6) latches the drive select biU, side
select
and
FM-!MFM bits on the rising
edge
of the control
sigtlal IDRVSEL -. A dual "0" flip-flop (U1B) is used to
latch the Wail Enable and Precompensation enable bits on
the rising edge of IDAVSEL -. The rising edge of JDAVSEL·
also triggers a one·shot (1/2 of U1S) which producese Motor
On to the disk drives. The duration of the Motor On signal
is approximately twO seconds. The spindle motors arc not
designed for continoU$ operation, therefore the inactive state
of the Motor On signal is used to clear the Drive Select Latch,
which dl!~lects any drives which were previously selected.
The Motor On one-sttot is retriggerable by simply exeQJting
an OUT instruction to the Drive Select latch.
The TA5-80 Modal III Floppy Disk Interface Board is an
optional board which if incorporated provides a standard five
inch floppy disk controller. The Floppy Disk Interface Board
supports both single and double density encoding schemes.
This flaturl, along with a special software packll!Je, al1ow~
the transfer of Model Idisk files to the Model III synem. This
resuhs in an upgrade to doubl~ density encoding for the
Model III owner. Write precompensation can be software
enabled or disabled beginning at any track, although the sys·
tern software enables write precompensation for all tracks
greater than twentY-one. The amount of write precompen·
sation is continously variable from I)nsec to rn()(e than 500
nsec. The write preoompensation is factory adjusted to 200
nsec. The data dock. recovery logic iflCOrporates a phase·
locked loop oscillator which achieves state of the
art
reliabl-
ity. One to four drives may be controlled by the interface
(two internal drives and two external). All data transfers are
accomplished by CPU data requests. In double density oper·
ation, data transfers are synchronized to the CPU by forcing
a walt to the CPU and clearing the wait by a data request
from the FDC chip. The end of the data transfer is indicated
by generating a non-rnaskable interrupt from the interrupt
request output of the FDC chip. A hilrdware watchdog timet:
insures that error conditions will not hang the wait line to
the CPU for a period long enough to destroy RAM contents.
The Floppy Disk Controller Board is an 110 port mapped
device which utilizes ports E4H, FOH, F1H, F2H, F3H, and
F4H. The decoding logic is implemented on the CPU board.
(See
the Decoding Logic section of the CPU discussion.) U4
of the Floppy Disk Controller Board is a non.inverting octal
buffer which isolates and buffers the required control signals.
Table 1 summarizes the port and bit allocation for the
Floppy Controller Board. U2 of the Floppy Disk Controller
Board is a bi-direc1ional. Bobit transceivef used to buffer data
to and from the Floppy Controllef Board. The direction of
data transfer is controlled by the combination of control sig-
nals DISKIN- and AONMIMASKREG-. If either sigrlill is
active (logic lowl. U2 is enabled 10 drive data onto the CPU
board data bus. If both signals are inactive (logic high). U2
is enabled to receive data from the CPU data bus.
Refer to the Schematic Diagram.
CONTROL AND DATA BUFFERING
NONMA5KABLE INTERRUPT LOGIC
A dual "0" "ip-flop (US) is used to latch data bits 06 and
07 on the rising edge of the control signal WRNM1MA5-
REG-. The outputs of US control the conditions which will
generate a non-maskable interrupt to the CPU. The NMI
interrupt oonditions are programmed by doing an OUT in·
struction to pon E4H with the appropriate bits set. If data
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