Panasonic JS-170FR Series Service Manual page 37

Pin No. Signal name
V 03 SD0
W 03 SD1
U 02 SD2
T 02 SD3
W 02 SD4
Y 02 SD5
T 01 SD6
V 01 SD7
W 16 SD8
T 16 SD9
Y 17 SD10
V 17 SD11
Y 18 SD12
W 18 SD13
Y 19 SD14
W 19 SD15
W 12 SBHE#
B 18 SDCS1#
C 18 SDCS3#
E 15 SDD0
B 15 SDD1
D 14 SDD2
C 14 SDD3
A 14 SDD4
C 13 SDD5
A 13 SDD6
C 12 SDD7
D 12 SDD8
B 13 SDD9
D 13 SDD10
B 14 SDD11
E 14 SDD12
A 15 SDD13
C 15 SDD14
D 15 SDD15
C 17 SDA0
B 17 SDA1
A 18 SDA2
A 17 SDDACK#
A 16 SDDREQ
C 16 SDIOR#
B 16 SDIOW#
D 16 SIORDY
A 06 SERR#
J 19 SERIRQ/GPI7
K 20 SLP#
N 17 SMBALERT#
R 19 SMBCLK
T 20 SMBDATA
U 03 SMEMW#
W 04 SMEMR#
P 20 SMI#
K 17 SPKR
D 05 STOP#
J 18 STPCLK#
IN/OUT
ISA system data bus.
IN/OUT
IN/OUT Used to indicate that SD8-SD15 of the ISA transfer data are effective. Active : Low
OUT The signal that becomes active with E-IDE's second I/O address 0170-0177h.
OUT The signal that becomes active with E-IDE's second I/O address.
E-IDE Secondary data bus.
IN/OUT
OUT E-IDE Secondary side address.
OUT E-IDE Acknowledge to secondary side PDDREQ.
IN E-IDE Secondary side DMA request signal.
OUT E-IDE Secondary side read signal.
OUT E-IDE Secondary side write signal.
IN E-IDE Secondary side ready signal.
IN/OUT PCI system error signal.
IN/OUT Serial bus interrupt signal.
OUT Sleep request signal to the PENTIUM II.
IN Interrupt signal for the system management bus.
IN/OUT Clock signal for the system management bus.
IN/OUT Serial data for the system management bus.
IN/OUT Write signal to the ISA 0-1Mbyte memory device.
IN/OUT Read signal to the ISA 0-1Mbyte memory device.
OUT Higher preference non-maskable interrupt. (→ CPU)
OUT Speaker output pin.
IN/OUT PCI Request signal from the target to the initiator for the suspension of execution.
OUT The signal used to specify the suspension of clock supply to CPU's internal core. (→ CPU)
2-7
Functions
Active : Low
Active : Low
Active : Low
Active : Low
Active : Low
Active : Low
Active : Low
Active : Low