Panasonic JS-170FR Series Service Manual page 35

Pin No. Signal name
H 20 IRQ0
J 20 IRQ1
T 09 IRQ3
W 09 IRQ4
U 08 IRQ5
V 08 IRQ6
Y 08 IRQ7
Y 20 IRQ8#/GPI6
U 01 IRQ9
U 12 IRQ10
W 13 IRQ11
T 13 IRQ12/M
V 14 IRQ14
Y 14 IRQ15
K 01 KBCCS#/GPO26
Y 15 LA17
T 14 LA18
W 14 LA19
U 13 LA20
V 13 LA21
Y 13 LA22
T 12 LA23
N 04 MCCS#
Y 12 MEMCS16#
V 15 MEMR#
U 15 MEMW#
L 20 NMI
J 01 OC0#
J 02 OC1#
V 11 OSC
B 06 PAR
D 11 PCICLK
E 10 PCIREQA#
A 11 PCIREQB#
B 11 PCIREQC#
C 11 PCIREQD#
A 01 PCIRST#
R 02 PCI_STP#
L 04 PCS0#
N 05 PCS1#
G 16 PDA0
G 18 PDA1
G 17 PDA2
H 17 PDCS1#
H 16 PDCS3#
F 20 PDD0
E 18 PDD1
E 20 PDD2
D 18 PDD3
D 20 PDD4
C 20 PDD5
B 20 PDD6
A 20 PDD7
IN/OUT
OUT System timer interrupt signal being output.
IN Mask enabled interrupt request signal. (← Keyboard controller)
IN Mask enabled interrupt request signal. (← Serial port 2)
IN Mask enabled interrupt request signal. (← Serial port 1)
IN Mask enabled interrupt request signal.
IN Mask enabled interrupt request signal. (← FDC)
IN Mask enabled interrupt request signal. (← Parallel port 1)
IN/OUT Mask enabled interrupt request signal. (← For RTC)
IN Mask enabled interrupt request signal. (← ETHERNET)
IN Mask enabled interrupt request signal. (← Serial port 4)
IN Mask enabled interrupt request signal. (← Serial port 3)
IN Mask enabled interrupt request signal. (← PS/2 mouse)
IN Mask enabled interrupt request signal. (← E-IDE)
IN Mask enabled interrupt request signal.
OUT Chip select signal to the keyboard controller.
IN/OUT ISA An address bus not latched yet.
OUT I/O An output that is active with I/O address 62h and 66h.
ISA Used to specify the data bus width of the memory. Low → 16-bit, High → 8-bit.
IN
IN/OUT ISA The read signal to the memory device. (All area)
IN/OUT ISA The write signal to the memory device. (All area)
OUT Non-maskable interrupt lower than SMI#. (→ CPU)
IN Overcurrent detector pin of the USB port.
IN Clock input for timer counter (8254). Fixed at 14.3181MHz.
OUT PCI PCI Bus parity signal.
IN PCI Clock signal for the PCI bus. 33MHz/30MHz
IN PCI Bus request signal.
OUT PCI Asynchronous reset signal.
OUT Clock stop request signal for PCI. (→ Clock synthesizer)
OUT Programmable chip select signal.
OUT E-IDE Primary side address.
OUT The signal that is active with I/O address 01F0-01F7h of E-IDE.
OUT The signal that is active with I/O address 03F6-03F6h of E-IDE.
E-IDE Primary data bus.
IN/OUT
2-5
Functions
Active : High
Active : High
Active : High
Active : High
Active : High
Active : High
Active : Low
Active : High
Active : High
Active : High
Active : High
Active : High
Active : High
Active : Low
Active : Low
Active : Low
Active : Low
Active : Low
Active : Low
Active : Low
Active : Low
Active : Low
Active : Low