Panasonic G600 Technical Manual page 31

VEGA
8.2.2 Downlink I and Q
DLIP
DLIN
DLQP
DLQN
Figure 3: Functional structure of the baseband downlink path
8.2.3 Power amplifier Ramp
The PA Ramp is formed by 2 D/As, The first, a 5 bit D/A defines the ramp shape, and the second − an 8 bit D/A
defines the maximum level.
The ramp shape is defined by 64 steps.The shape can be defined differently for rising and falling ramps. Typically a
raised cosine shape will be used as a starting basis of the ramp shape.
35.00
30.00
25.00
20.00
15.00
10.00
5.00
0.00
Figure 4: Example for the PA ramp
The raised cosine shape will be modified to compensate for RF circuit characteristics.
The ramp time is selectable between each step being 1/16 of a bit and each step being 1/8 of a bit giving a
maximum ramp time of either 14.77µS or 29.53µS.
An 8 bit value is used to program the ramp output level.
Issue 1
Revision 0
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Offset
Calibration
Antialiasing Sigma_Delta
Filter Modulator
fs1=6.5 Mhz
Antialiasing Sigma_Delta
Modulator
Filter
Offset
Calibration
Ramp Down
Step
Offset
Register
SINC
FIR
Filter
Filter
fs2=1.08 Mhz fs3=270.8 Khz
SINC
FIR
Filter
Filter
Offset
Register
35.00
30.00
25.00
20.00
15.00
10.00
5.00
0.00
Section 8
8 - 2
SUB
To baseband
serial
interface
SUB
600-0803
Ramp Up
Step
600-0804
MCUK980101G8
Technical Guide