Daewoo DUB-2850GB Service Manual page 46

CP-780 Service Manual
5.2.9 Colour decoder
The ICs decode PAL, NTSC and SECAM signals. The PAL/NTSC decoder does not need
external reference crystals but has an internal clock generator which is stabilised to the required
frequency by using the clock signal from the reference oscillator of the TCG u -Controller.
Under bad-signal conditions (e.g. VCR-playback n feature mode), it may occur that the colour
killer is activated although the colour PLL is still in lock. When this killing action is not wanted it
is possible to overrule the colour killer by forcing the colour decoder to the required standard
and to activate the FCO-bit (Forced Colour On) in subaddress3CH. The sensitivity of the colour
decoder for PAL and NTSC can be increased by means of the setting of the CHSE1/CHSE0
bits in subaddress 3CH.
The Automatic Colour Limiting (ACL) circuit (switchable via the ACL bit in subaddress 3BH)
prevents that oversaturation occurs when signals with a high chroma-to-burst ratio are received.
The ACL circuit is designed such that it only reduces the chroma signal and not the burst signal.
This has the advantage that the colour sensitivity is not affected by this function.
The SECAM decoder contains an auto-calibrating PLL demodulator which has two references,
viz: the divided reference frequency (obtained from the-Controller) which is used to tune the
PLL to the desired free-running frequency and the bandgap reference to obtain the correct
absolute value of the output signal. The VCO of the PLL is calibrated during each vertical
blanking period, when the IC is in search or SECAM mode. The frequency offset of the B-Y
demodulator can be reduced by means of the SBO1/SBO0 bits in subaddress 3CH.
The base-band delay line is integrated. In devices without CVBS comb filter this delay line is
also active during NTSC to obtain a good suppression of cross colour effects. The demodulated
colour difference signals are internally supplied to the delay line. The baseband comb filter can
be switched off by means of the BPS bit (subaddress 3CH).
The subcarrier output is combined with a 3-level output switch (0 V, 2.1 V and 4.5 V). The
output level and the availability of the subcarrier signal is controlled by the CMB2-CMB0 bits.
5.2.10 RGB output circuit
In the RGB control circuit the signal is controlled on contrast, brightness and saturation. The IC
has a YUV interface so that additional picture improvement ICs can be applied. To compensate
signal delays in the external YUV path the clamp pulse in the control circuit can be shifted by
means of the CLD bit in subaddress 44H. When the YUV interface is not required some of the
pins can be used for the insertion of RGB/YPrPb signals or as additional CVBS(Y)/C input.
When the YUV interface is not used one of the pins (VOUT) is transferred to general purpose
output switch (SWO1). The IC has also a YUV interface to the digital die. Via this loop digital
features like double window are added.
A tint control is available for the base-band U/V signals. For this reason this tint control can be
activated for all colour standards. The signals for OSD and text are internally supplied to the
control circuit. The output signal has an amplitude of about 1.2V black-to-white at nominal input
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