HP 7942 Service Manual page 38

Theory of Operation
7942
and
7946
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Figure 3-2. Track Recording Format
3-4. HOC PCA-AS
Host dependent controller PCA-A5 provides an in-
terface between the host computer and the device
dependent controller (DDC) of the disc drive. (The
HDC is also capable of interfacing with the DDC
of a second mass storage device.) The common
functions required for the two mass storage devices
are consolidated in the HDC leaving the device
dependent tasks (servo control, read, write, data
separation, data generation, etc.) to the DDC's.
Host dependent controller interface with the host
is via the Hewlett-Packard Interface Bus (HP-IB)
and with the DDC's via the HDC's Data/Control
Interface Bus (DC-IB).
Host dependent controller functions include:
• A host interface via the HP-IB.
• Direct memory access (DMA) capability.
• A random access memory (RAM) buffer for
data examination for integrity, error correc-
tion, and speed matching between devices.
• Firmware for a microprocessor to execute
DDC commands and monitor status.
• Self -test diagnostic capabilities.
Circuits in host dependent controller PCA - A 5 (see
figure 3-5) include an HP-IB interface IC, a mic-
roprocessor, firmware in EPROM, RAM, a custom-
designed DMA gate array IC, and self -test switches
and display.
3-6
The firmware in the HDC consists of three seg-
ments. One segment is the executive operating sys-
tem (EXEC EPROM) which controls resource al-
location (including the DMA gate array IC and
RAM), and the passing of messages and informa-
tion between the DDC firmware and the host in-
terface firmware. The remaining two segments
comprise the control firmware for the two mass
storage devices (DDC 0 and DDC 1). The micro-
processor is shared between the two sets of DDC
firmware and the executive firmware by timeshar-
ing, each receiving the microprocessor for ap-
proximately 0.5 millisecond. Each set of firmware
takes care of its own task, performing whatever
function the host or device has requested. Self -test
firmware is included in each of the three segments.
The DDC's communicate with the HDC over the
DC-IB. This bus contains an 8-bit control/status
data bus with appropriate read/write strobes and
associated 6 - bit control/status address bus, and a
completely independent 8-bit read/write data bus
with associated strobes.
The following paragraphs provide a more detailed
description of the host dependent controller cir-
cuitry, as shown on the disc drive functional block
diagram, sheet _ . Refer to table 3-1 for a de-
scription of the mnemonics used in the text and on
sheet _
3-5. HDC INTERNAL BUS ARCHITECTURE
The internal bus architecture of the HDC consists
of the following buses: