Schematic Diagram; Main Assy (1/2) - Pioneer CDJ-400 Service Manual

1

10. SCHEMATIC DIAGRAM

10.1 MAIN ASSY (1/2)

A
!
The mark found on some component parts should be replaced
with same parts (safety regulation authorized) of identical
designation
NOTES
NM means STANDBY
RS1/16SS***J
RS1/16SS****F
F
RS1/16SS****D
D
CKSSYB
CCSSCH
CH
CEVW or CEHVW
V+3R3
B
GNDD GNDD
1 2
RSVD TMSBKPT
3 4
GNDD TCKDS
5 6
GNDD RSVD
7 8
TDIDSI
XRST
9 1 0
TDODSO
V+3R3
1 1 1 2
PST3
GNDD
1 3 1 4
PST1
PST2
1 5 1 6
DT3
PST0
1 7 1 8
DT1
DT2
1 9 2 0
GNDD
DT0
2 1 22
RSVD RSVD
23 24
GNDD PSTCLK
25 26
V+3R3 TA
27 28
GNDD GNDD
29 30
GNDD
FLASH ROM(16M)
V+3R3
C
IC101
4 8 1
DYW1763-
A 1 6 A 1 5
4 7 2
/ B Y T E A 1 4
S29AL016D70TFI010
4 6 3
V S S _ 4 6 A 1 3
4 5 4
DATA15
D Q 1 5 _ A - 1 A 1 2
DATA7 4 4 5
D Q 7 A 1 1
4 3 6
DATA14
D Q 1 4 A 1 0
4 2 7
DATA6
D Q 6 A 9
DATA13 4 1 8
D Q 1 3 A 8
4 0 9
DATA5
D Q 5 A 1 9
3 9 1 0
DATA12
D Q 1 2 N C 1 0
3 8 1 1
DATA4
X W E
D Q 4 / W E
C 1 0 1
3 7 1 2
From CPU
V C C _ 3 7 / R E S E T
0.1u
DATA11 3 6 1 3
D Q 1 1 N C 1 3
3 5 1 4
DATA3
R 1 0 2
D Q 3 N C 1 4
3 4 1 5
DATA10 2 2 k
D Q 1 0 R Y _ / B Y
DATA2 3 3 1 6
D Q 2 A 1 8
3 2 1 7
DATA9
D Q 9 A 1 7
DATA1 3 1 1 8
D Q 1 A 7
3 0 1 9
DATA8
D Q 8 A 6
2 9 2 0
DATA0
D Q 0 A 5
2 8 2 1
X O E
/ O E A 4
2 7 2 2
From CPU
V S S _ 2 7 A 3
2 6 2 3
GNDD / C E A 2
2 5 2 4
A 0 A 1
D
XCSFLASH
R 1 0 3
2 2 k
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
IC102
48
-b
C 1 0 5
54 1
GNDD
VSS3 V D D 1 0.1u
53
DATA15 2
DQ15 D Q 0
C 1 0 6
52 3
VSSQ4 V D D Q 1
0.1u
51 4
DATA14
DQ14 D Q 1
50 5
DATA13
DQ13 D Q 2
C 1 0 2
49 6
VDDQ4 V S S Q 1
0.1u
DATA12 4 8 7
D Q 1 2 D Q 3
4 7 8
DATA11
D Q 1 1 D Q 4
C 1 0 7
4 6 9
V S S Q 3 V D D Q 2
0.1u
DATA10 4 5 1 0
D Q 1 0 D Q 5
4 4 1 1
DATA9
D Q 9 D Q 6
C 1 0 3
4 3 1 2
V D D Q 3 V S S Q 2
0.1u
4 2 1 3
DATA8
D Q 8 D Q 7
C 1 0 8
4 1 1 4
V S S 2 V D D 2
0.1u
4 0 1 5
GNDD
E 70MHz
N . C / R F U L D Q M
3 9 1 6
UDQM XWESDRAM
U D Q M W E
C L K _ 7 0 M
3 8 1 7
C L K C A S
3 7 1 8
BCLKE R 1 0 4
From CPU
C K E R A S
3 6 1 9
XCSSDRAM
A 1 2 C S
46 2 2 k
-b 3 5 2 0
A 1 1 B A 0
3 4 2 1
A 9 B A 1
3 3 2 2
A 8 A 1 0 / A P
3 2 2 3
A 7 A 0
3 1 2 4
A 6 A 1
3 0 2 5
A 5 A 2
2 9 2 6
A 4 A 3
C 1 0 9
2 7
2 8
V S S 1 V D D 3
0.1u
K4S561632H-UC75
GNDD
SDRAM(256M)
F
A 1/2
50
1
2
5.0V
REGULATOR
V+7M V+5A
!
IC119
V+5A
1 5
V i n V o u t
2
G N D
3 4
C O N T R O L N B
21
NJM2872BF05
22
(Data)
DACLRCK
DACDATA
C 2 1 1
23
DACBCK
1 0 0 u / 1 6
V+3R3A C 2 0 4
0.1u
25
GNDD
11M
TMSBKPT CLK_DAC11M
24
TCKDS SPDIF0
CLK_DSP16M
16.9344M
TDIDSI
TDODSO
D S P D R E Q
PST3
to CPU&FPGA
PST1
VALID
DBCK
6 1
PSTCLK
PE3
6 2
TA BCK
6 3
C 1 1 0
6 4
0.1u
6 5
H C K T _ P E 5
6 6
PST0
H C K R _ P E 2
6 7
PST2
C O R E _ G N D _ 4
6 8
R 1 0 9
XRST SPDIF0
A D O _ P D 1
6 9
2 . 7 k
A C I _ P D 0
7 0
C 1 1 1
C O R E _ V D D _ 4
7 1
0.1u
H C K R _ P C 2
7 2
32
CLK_DAC11M
H C K T _ P C 5
7 3
I O _ G N D _ 5
7 4
C 1 1 2
I O _ V D D _ 5
7 5
0.1u
BCK
ADRS17
7 6
DACBCK
7 7
ADRS16 DBCK
7 8
ADRS15 DACLRCK
7 9
ADRS14 DATAL1
8 0
ADRS13
33
ADRS12
34
35
ADRS11
ADRS10
ADRS9
ADRS20
DATAR1
DATAL2
DATAR2
DSP-DAC
RX/XBY
ADRS19
ADRS18
ADRS8
DATAR2
ADRS7
DATAL2
ADRS6
ADRS5
ADRS4
ADRS3
ADRS2
ADRS1
V+2R5
R 1 0 7 R 1 1 2
N M
0
STBY
GNDD
DATAR1
DATAL1
DBCK
VALID
0.1
C 1 1 8
0.1
48
-a
C 1 1 9
CLK_DSP16M 16.9344M
BCK
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
0.1
C 1 2 0
0.1
C 1 2 1
DATA6
DATA7
X O E
LDQM From CPU
XCAS 47
XRAS
ADRS23
ADRS25
ADRS22
49
ADRS16
GNDD
ADRS15
ADRS14
V+2R5
ADRS13
V2R5
IC104
!
ADRS12
1
ADRS11
V o u t
ADRS10
2
N C
ADRS9
3
ADRS18 G N D
4
ADRS19
C n
ADRS20
MM1562FF
ADRS21
BCLKE
GNDD
UDQM
REGULATOR
2
3
3.3V
REGULATOR
V+3R3A
! IC120
1 5
FILTER
V I N V O U T
2
G N D
20
3 4
C O N T R O L N B
NJM2872BF33
(Anal)
ALO
R 1 2 5 R 1 3 1
A_ALOUT0
4 7 0 D 1 . 5 k
A_AROUT0
AUDIO
C 1 4 8
FILTER GNDD 470p
R 1 2 7
DAC
1 0 k
ARO
R 1 2 4 R 1 2 8
1 . 5 k
4 7 0 D
C 1 4 7
Q S P I S O 26
GNDD
470p
From CPU
Q S P I S C K
V-5
From CPU
ZERO
DACCS
28
DSP16M
16.9344M
27
DSPRST
29
4 0
C 1 4 0
3 9
0.1u
3 8
S S _ H A 2 3 7
S C K _ S C L
3 6
61: 40: M I S O _ S D A
F S R _ P E 1 P L L A _ G N D 3 5
62: S C K T _ P E 3 39: P L L A _ V D D
M O S I _ H A 0
3 4
63: S C K R _ P E 0 38: H R E Q TMS
T M S 3 3
64: I O _ V D D _ 4 TCK
T C K 3 2
65: I O _ G N D _ 4
IC105 TDI
T D I
3 1
TDO
DSPC56371AF180
T D O
3 0
C 1 4 1
76: S C K R _ P C 0 C O R E _ V D D _ 2
2 9
0.1u
77: S C K T _ P C 3 DSP
C O R E _ G N D _ 2 2 8
78: F S R _ P C 1
T I O 1 _ P B 1 2 7 GNDD
F S T _ P C 4
79:
80: S D O 5 _ S D I 0 _ P C 6
T I O 0 _ P B 0 2 6
23: P F 1 0 C 1 4 2
I O _ V D D _ 3
22: S C A N 2 5
0.1u
21: P F 9
I O _ G N D _ 3
2 4
2 3
R 1 2 6
2 2
2 2 k
PF9
2 1
(Data)
GNDD
CPU-FPGA
37
TDI
1
2
3
4
I O _ L 2 1 P _ 7
5
I O _ L 2 1 N _ 7
6
V C C O _ 7
7
V C C A U X 1
1: I O _ L 0 1 P _ 7 / V R N _ 7 I O _ L 0 1 N _ 2 / V R P _ 2
8 75:
I O _ L 2 3 P _ 7
2:
I O _ L 0 1 N _ 7 / V R P _ 7 74: I O _ L 0 1 P _ 2 / V R N _ 2
9
I O _ L 2 3 N _ 7
3: G N D 1
1 0
G N D 2
1 1
FPGA
I O _ L 4 0 P _ 7
1 2
I O _ L 4 0 N _ 7 / V R E F _ 7 I O _ L 4 0 P _ 2 / V R E F _ 2
1 3
I O _ L 4 0 P _ 6 / V R E F _ 6 I O _ L 4 0 N _ 3 / V R E F _ 3
IC106
1 4
I O _ L 4 0 N _ 6
XC3S50-4VQG100C
1 5
I O _ L 2 4 P _ 6
1 6
I O _ L 2 4 N _ 6 / V R E F _ 6
1 7
22: I O _ L 0 1 P _ 6 / V R N _ 6
I O 1
1 8
23: I O _ L 0 1 N _ 6 / V R P _ 6
V C C I N T 1
24: M 1
1 9
V C C O _ 6
25: M 0
2 0
G N D 3
2 1
I O 2
2 2
I O _ L 0 1 N _ 3 / V R P _ 3
2 3
I O _ L 0 1 P _ 3 / V R N _ 3
2 4
2 5
46
-a
V+3R3
V3R3
7
V i n
6
S u b
5
C o n t
GNDD
2.5V
70MHz
19
-a
CDJ-400
3
4
R 1 3 0
1 0 k D
C 2 0 5
R 1 3 6
1 0 0 u / 1 6
C 1 5 1
1 1 k D
0.1u
C 2 0 9
(Anal)
D
560p GNDD
6
8 Lch
7
I C 1 0 7
4
NJM4580MD
5
R 1 3 5
D 1 1 k D
C 2 1 0
D
560p
I C 1 0 7
2 NJM4580MD
Rch
8
1
C 1 4 9
4
3
0.1u
C 2 1 2
GNDD
1 0 0 u / 1 6
V+3R3
C 1 6 1
0.01u
C 1 6 2
1 0 0 u / 6 . 3
GNDD
SPD1
V+1R25
Q 1 0 2
2 S C 2 4 1 2 K ( R S )
SPDIF0 SPD0
V+3R3
GNDD
V+3R3
R T 1 N 2 4 1 M
R T 1 P 2 4 1 M
31
Q 1 0 3
Q 1 0 1
MUTE
CURCUIT
30
V-5
IC110
BD00KA5WFP-TLB
V+1R25
!
V+3R3
V1R25
1.25V
REGULATOR
GNDD
CPU-DSP-DAC
CPU-BUS
IC108
V+3R3 V+1R2
BD00KA5WFP-TLB
!
V3R3 V1R2
SRVSCLK
PWMSL1IN
PWMSL2IN
GNDD
1.2V
TDO
REGULATOR
7 5
7 4
SRVSDATA
7 3
G N D 8
7 2
SRVLRCK
I O _ L 2 1 N _ 2
7 1
I O _ L 2 1 P _ 2 S R V S B S Y
0.1
7 0 From SRV
C 1 5 2
V C C O _ 2
A 2/2
0.1
6 9
C 1 5 3
V C C I N T 3
6 8 PWMLO
I O _ L 2 4 N _ 2
6 7
XFRST
I O _ L 2 4 P _ 2
C 2 2 0
6 6
G N D 7
6 5 0.1u
FPGALRCK
38
I O _ L 4 0 N _ 2
6 4
FPGASCLK
6 3 FPGASDATA
6 2
FPGASBSY
I O _ L 4 0 P _ 3
From CPU
6 1
X W E
I O _ L 2 4 N _ 3
6 0 FPGADREQ
I O _ L 2 4 P _ 3
5 9 From DSP
I O 4 D S P D R E Q
0.1
5 8
V C C A U X 3 C 1 5 4 39
5 7
C 1 5 5
V C C O _ 3
5 6 0.1
G N D 6
5 5 XCSFPGA
I O 3
5 4
ADRS1
5 3
ADRS2
5 2 R 1 3 9
Q S P I S C K 41
C C L K
5 1 From CPU
4 7 0
D O N E
40
XINIT
2
V+3R3
C 1 6 3
42
V+3R3
R 1 4 8
C 1 5 7
0.1
5
V C C
IC109
16M
CPU16M 4
8 V C C 1 A 1
O U T Y
7 3 Y 2
43
1 Y
TC7SU04FU
6 2 A 3
3 A
CLK_FP16M
5 4
2 Y G N D
FP16M
45
TC7W04FU-TRB
44
V S S 1 0 8 4 - A
GNDD 16.9344MHz
OSC
ADRESS
DATA
4
V+3R3
C 2 0 8
OSC 0.1
TC7SU04FU
IC117
1 5
N C V C C
6M0
2 I N A
3 4
G N D
O U T Y
R198
1M
X102
VSS1210-A
6MHz
GNDD
Q S P I S C K
From CPU
Q S P I S O
From CPU
0.1
1M
1
N C
I N A 2
3
G N D
IC111
X 1 0 1
GNDD