Beko LM CHASSIS Service Manual page 22

GPO Interface
Pin Name Pin Type
PWM0 Output
PWM1 Output
PWM2 Output
PWM3/GPO[7] Output
PWM4/GPO[8] Output
PWM5/GPO[9] Output
GPO[6:0] Output
DRAM Interface
Pin Name Pin Type
MVREF Input
MCLKE Output
MCLKZ Output
MCLK Output
RASZ Output
CASZ Output
WEZ Output
DQM[1:0] Output
DQS[3:0] Output
BADR[1:0] Output
MADR[11:0] Output
MDATA[31:0] I/O
Misc. Interface
Pin Name Pin Type
DDCD_DA I/O w/ 5V-tolerant
DDCD_CK Input w/ 5V-tolerant
DDCR_CK Input w/ 5V-tolerant
DDCR_DA I/O w/ 5V-tolerant
BYPASS
Version 1.0
SXGA/WXGA LCD Multi-Function Monitor Controller with Dual LVDS Transmitter
Function
PWM; 4mA driving strength
PWM; 4mA driving strength
PWM; 4mA driving strength
GPO with PWM Function; 6mA driving strength
GPO with PWM Function; 6mA driving strength
GPO with PWM Function; 6mA driving strength
GPO; 6mA driving strength
Function
Reference Voltage for DDR SDRAM Interface
DRAM Memory Clock Enable
DRAM Memory Clock Complementary / Input
(for differential clocks)
DRAM Memory Clock
Row Address Strobe, active low
Column Address Strobe, active low
Write Enable, active low
Data Mask Byte Enable
Data Strobe
Memory Bank Address
Memory Address
Memory Data
Function
HDCP Serial Bus Data / DDC Data of DVI Port; 4mA driving
strength
HDCP Serial Bus Data / DDC Clock of DVI Port
DDC Clock for ROM
DDC Data for ROM
For External Bypass Capacitor
Copyright © 2006 MStar Semiconductor, Inc. All rights reserved.
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MST6181LDA
Product Brief Version 1.0
Pin
252
253
98
188
189
190
186-184,
179-176
Pin
124
125
126
127
132
135
136
121, 153
101, 120, 154, 173
130, 131
150-147, 144-137
102-105, 108-119,
155-158, 161-172
Pin
18
19
94
97
192
1/12/2006