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RXD-V252/V252-H
Port Function of MPEG1 Video/Audio Processing : ES3880 (ICM2)
Port No.
1,31,51
2
3
4~12
13~28
29
30,50,80,100
32~39
40
41
42
43
44
45~49,52,53,54
55~62
63
64
65,66,67
68~79,82~87
81
88
89
AOUT/SEL/PLL0
90
91
ATFS/SEL/PLL1
92
93
94
95
96
97
98
99
Block Diagram for MPEG1 Video/Audio Processing
Processor
LA(17:0)
Interface
LD(7:0)
LCS3#, LCS#(1:0)
LWR#
LOE#
ACLK
Serial
ATCLK
Audio
AIN
Interface
AOUT
ARFS
ATFS
ARCLK
TDM
SEL
PLL(1:0)
-
Interface
TDMCLK
TDMDR
TDMFS
4
CIRCUIT DESCRIPTION
Port Name
I/O
VCC3
-
Supply voltage for 3.3V.
RAS#
O
DRAM row address strobe (active low).
DWE#
O
DRAM write enable (active low).
MA(0~8)
O
DRAM multiplexed row and column address bus.
DBUS(0~15)
I/O
DRAM data bus.
RESET#
I
System reset (active low).
GND
-
Ground.
Y is luminance, UV are chrominance data bus for screen video interface.
YUV(0~7)
O
YUV(0~7) for 8 bit YUV mode.
Vertical sync for screen video interface, programmable for rising or
VSYNC
I/O
falling edge.
Horizontal sync for screen video interface, programmable for rising or
HSYNC
I/O
falling edge.
CPUCLK
I
RISC and system clock input.
PCLK2X
I/O
Pixel clock: two times the actual pixel clock for screen video interface.
PCLK
I/O
Pixel clock qualifier in for screen video interface.
AUX(0~7)
I/O
Auxiliary control pins (AUX0 and AUX1are open collectors).
LD(0~7)
I/O
RISC interface data bus.
LWR#
O
Unused.
LOE#
O
RISC interface output enable (active low).
LCS(3,1,0)#
O
RISC interface chip select (active low).
LA(0~17)
O
RISC interface address bus.
VCC
-
Digital supply voltage for 5.0V.
Master clock for external audio DAC(8.192MHz, 11.2896MHz, 12.288MHz,
ACLK
I/O
16.9344MHz, and 18.432MHz).
O
Dual-purpose pin. AOUT is the audio interface serial data output.
Pins SEL -PLL(1: 0) select phase-lock loop(PLL) clock frequency
I
CPUCLK for the Visba : 00 = bypass PLL 01 = 54MHz PLL
10 = 67.5MHz PLL 11 = 81MHz PLL
ATCLK
I/O
Audio transmit bit clock.
O
Dual-purpose pin. ATFS is the audio interface transmit frame sync.
Pins SEL -PLL(1: 0) select phase-lock loop(PLL) clock frequency CPUCLK
I
for the Visba. See the SEL -PLL0 pin above for the settings.
Dual-purpose pin. DRAM output enable (active low)/DRAM multiplexed
DOE
O
row and column address bus.
AIN
I
Audio interface serial data input.
ARCLK
I
Audio receive bit clock.
ARFS
I
Audio interface receive frame sync.
TDMCLK
I
TDM interface serial clock.
TDMDR
I
TDM interface serial data receive.
TDMFS
I
TDM interface frame sync.
CAS#
O
DRAM column address strobe bank 0 (active low).
Huffman
Decoder
RISC
Processor
Serial Audio
Interface
64x32 ROM
32x32 SRAM
Registers
TDM
Interface
DRAM Interface
2Kx32 ROM
2x32 SRAM
MPEG
Processor
Video Output
On Screen
Display
DRAM DMA
Controller
Function
RAS#
DA(8:0)
DBUS(15:1)
DOU#
DRAM
DWE#
CAS#
AUX
AUX(7:1)
YUV(7:0)
Screen
PCLK2X
PCLK
VSYNC
HSYNC
CPUCLK
Misc
RESET#
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