MSI MS-6378 ATX User Manual page 57

Chapter 3
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait state.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
PCI #2 Access #1 Retry
When Disabled, PCI#2 will not be disconnected until access finishes.
When Enabled, PCI#2 will be disconnected if max retries are attempted
without success.
AGP Master 1 WS Write
When Enabled, writes to the AGP bus are executed with one wait state
inserted.
AGP Master 1 WS Read
When Enabled, one wait state is inserted in the AGP read cycle.
Memory Parity/ECC Check
User can set the field to Enabled for memory checking if the type of DRAM
installed in your system is Parity or ECC (Error-Correcting Code) DRAM.
AGP Master 1 WS Write
When Enabled, writes to the AGP bus are executed with one wait state
inserted.
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