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Part Number 405CPU

Revision 1.02 - September 10, 2007

405

Preliminary User's Manual

PPC405 Processor

User's Manual

AMCC Proprietary

Table of Contents

Summary of Contents for AMCC PPC405

Page 1 Part Number 405CPU Revision 1.02 - September 10, 2007 Preliminary User’s Manual PPC405 Processor PPC405 Processor User’s Manual AMCC Proprietary...
Page 2 AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
Page 3: Table Of Contents
1. Overview ............................21 1.1 PPC405 Processor Features ........................21 1.2 PowerPC Architecture ..........................22 1.3 PPC405 as a PowerPC Implementation ....................23 1.4 RISC Processor Core Organization ......................23 1.4.1 Instruction and Data Cache Controllers ..................23 1.4.1.1 Instruction Cache Unit ......................23 1.4.1.2 Data Cache Unit ........................
Page 4 2.7.5 Branch Prediction ..........................52 2.8 Speculative Accesses ..........................53 2.8.1 Speculative Accesses in the PPC405 ..................... 53 2.8.1.1 Prefetch Distance Down an Unresolved Branch Path ............. 54 2.8.1.2 Prefetch of Branches to the CTR and Branches to the LR ............54 2.8.2 Preventing Inappropriate Speculative Accesses ................
Page 5 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 2.11.6.4 Cache Management Instructions ................... 66 2.11.7 Interrupt Control Instructions ......................66 2.11.8 TLB Management Instructions ...................... 66 2.11.9 Processor Control Instructions ...................... 67 2.11.10 Extended Mnemonics ........................67 3.
Page 6 5.8.1.6 Storage Little-Endian Register (SLER) .................. 107 6. Interrupt Handling ......................... 109 6.1 Architectural Definitions and Behavior ....................109 6.2 Behavior of the PPC405 Implementation ....................110 6.3 Interrupt Handling Priorities ........................111 6.4 Critical and Noncritical Interrupts ......................112 6.5 General Interrupt Handling Registers .....................
Page 7 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 6.14 Programmable Interval Timer (PIT) Interrupt ..................125 6.15 Fixed Interval Timer (FIT) Interrupt ....................... 125 6.16 Watchdog Timer Interrupt ........................126 6.17 Data TLB Miss Interrupt ........................127 6.18 Instruction TLB Miss Interrupt .......................
Page 8 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 8.8.13.1 DAC Exact Address Compare ..................... 150 8.8.13.2 DAC Range Address Compare .................... 151 8.8.13.3 DAC Applied to Cache Instructions ..................152 8.8.13.4 DAC Applied to String Instructions ..................153 8.8.14 Data Value Compare Debug Event .....................
Page 9 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual B.12 Interrupt Control Instructions ....................... 427 B.13 TLB Management Instructions ......................428 B.14 Processor Management Instructions ....................429 Appendix C. Code Optimization and Instruction Timings ............430 C.1 Code Optimization Guidelines ......................430 C.1.1 Condition Register Bits for Boolean Variables ................
Page 10: Ppc405 Processor Revision 1.02 - September
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual AMCC Proprietary...
Page 11: Figures
Figure 2-9. Condition Register (CR) ........................40 Figure 2-10. PPC405 Data Types ........................42 Figure 2-11. Normal Word Load or Store (Big Endian Storage Region) .............. 48 Figure 2-12. Byte-Reverse Word Load or Store (Little Endian Storage Region) ..........48 Figure 2-13.
Page 12 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Figure 8-1. Debug Control Register 0 (DBCR0) ....................143 Figure 8-2. Debug Control Register 1 (DBCR1) ....................144 Figure 8-3. Debug Status Register (DBSR) .....................145 Figure 8-4. Instruction Address Compare Registers (IAC1–IAC4) ..............147 Figure 8-5.
Page 13: Tables
Conditional Branch BO Field ......................52 Table 2-10. Example Memory Mapping ......................55 Table 2-11. Privileged Instructions ........................57 Table 2-12. PPC405 Instruction Set Summary ....................61 Table 2-13. Implementation-specific Instructions ....................62 Table 2-14. Storage Reference Instructions ....................... 62 Table 2-15.
Page 14 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table 6-9. Register Settings during External Interrupts ..................122 Table 6-10. Alignment Interrupt Summary ......................123 Table 6-11. Register Settings during Alignment Interrupts ................123 Table 6-12. ESR Usage for Program Interrupts ....................123 Table 6-13.
Page 15 Table 9-34. Extended Mnemonics for tw ......................342 Table 9-35. Extended Mnemonics for twi ......................345 Table 10-1. PPC405 General Purpose Registers ..................... 353 Table 10-2. PPC405 General Purpose Registers ..................... 353 Table 10-3. Special Purpose Registers ......................354 Table 10-4.
Page 16: Ppc405 Processor Revision 1.02 - September
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual AMCC Proprietary...
Page 17: About This Book
About This Book This user’s manual provides the architectural overview, programming model, and detailed information about the registers, the instruction set, and operations of the AMCC PowerPC™ 405 (PPC405) embedded processor. This device contains a 32-bit reduced instruction set computer (RISC) processor.
Page 18 Revision 1.02 - September 10, 2007 Preliminary User’s Manual How to Use This Book This book describes the PPC405 device architecture, programming model, external interfaces, internal registers, and instruction set. This book is organized as follows: • Overview on page 21 •...
Page 19 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Conventions The following is a list of notational conventions frequently used in this manual. ActiveLow An overbar indicates an active-low signal. A decimal number A hexadecimal number A binary number Assignment ∧...
Page 20 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual General Purpose Register (GPR) r, where 0 ≤ r ≤ 31. GPR(r) The contents of GPR r, where 0 ≤ r ≤ 31. (GPR(r)) mfdcr mtdcr DCR(DCRN) A Device Control Register (DCR) specified by the DCRF field in an...
Page 21: Overview
This section describes: • PPC405 processor features • PPC405 as a 32-bit implementation of Book-E Enhanced PowerPC Architecture. • Organization of the PPC405 core, including a block diagram and descriptions of the functional units. • PPC405 core interfaces. 1.1 PPC405 Processor Features The PPC405 provides high performance and low-power consumption executing at sustained speeds approaching one cycle per instruction.
Page 22: Powerpc Architecture
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual • Page-level access control using the translation mechanism • Software control of page replacement strategy • Additional control over protection using zones • WIU0GE (write-through, cachability, compressed user-defined 0, guarded, endian) storage attribute control for each virtual memory region •...
Page 23: Ppc405 As A Powerpc Implementation
1.4.1 Instruction and Data Cache Controllers The PPC405 processor core uses a 16-KB instruction cache unit (ICU) and an 16-KB data cache unit (DCU) to enable concurrent accesses and minimize pipeline stalls. Both cache units are two-way set-associative and use a 32-byte line size.
Page 24: Memory Management Unit
• Additional control over protection using zones • Storage attributes for cache policy and speculative memory access control The MMU can be disabled under software control. If the MMU is not used, the PPC405 provides other storage control mechanisms. The translation lookaside buffer (TLB) is the hardware resource that controls translation and protection. It consists of 64 entries, each specifying a page to be translated.
Page 25: Debug
Each storage attribute control register contains 32 fields. Each field sets the associated storage attribute for a 128MB memory region. See the topic Real-Mode Storage Attribute Control in the PPC405 Processor User’s Manual for details about the storage attribute control registers.
Page 26: Processor Core Interfaces
JTAG hardware for boundary-scan system testing. 1.4.4.5 Interrupts The PPC405 provides an interface to the UIC, an on-chip interrupt controller that is logically outside the processor. The UIC combines asynchronous interrupt inputs from on-chip and off-chip sources and presents them to the processor core using a pair of interrupt signals: critical and non-critical.
Page 27: Processor Register Set Summary
1.5.2.3 Machine State Register The PPC405 processor core contains a 32-bit Machine State Register (MSR). The contents of a GPR can be written to the MSR using the mtmsr instruction, and the MSR contents can be read into a GPR using the mfmsr instruction.
Page 28: Memory-Mapped I/O Registers
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 1.5.3 Memory-Mapped I/O Registers The memory-mapped I/O (MMIO) registers are accessed using load and store instructions. MMIO registers, which are outside processor core and which are not architected, are used to control, configure, and hold status for various functional units that are not part of the processor core.
Page 29 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual AMCC Proprietary...
Page 30 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual AMCC Proprietary...
Page 31: Programming Model
2.1 User and Privileged Programming Models The PPC405 executes programs in two modes, also referred to as states. Programs running in privileged mode (also referred to as the supervisor state) can access any register and execute any instruction. These instructions and registers comprise the privileged programming model.
Page 32: Storage Attributes
(the U0 storage attribute) and byte ordering (the E storage attribute). The PPC405 provides two control mechanisms for the W, I, U0, G, and E attributes. Because the PPC405 does not provide hardware support for multiprocessor environments, the M storage attribute, when present, has no effect.
Page 33 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Programming Note: Programming Note: A good coding practice is to perform the initial write to a register with reserved fields as described, and to perform all subsequent writes to the register using a read-modify- write strategy: read the register, use logical instructions to alter defined fields, leaving reserved fields unmodified, and write the register.
Page 34: Figure 2-2. Ppc405 Programming Model-Registers
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Figure 2-1. PPC405 Programming Model—Registers Supervisor Model User Model General-Purpose Registers Machine State Register Processor Version Register GPR0 SPR 0x11F GPR1 Core Configuration Register Timer Facilities • Time Base Registers...
Page 35: General Purpose Registers (Gpr0-Gpr31)
Table 10-3 on page 354 shows the mnemonic, name, and number for each SPR. Table 2-1 on page 36, lists the PPC405 SPRs by function and indicates the pages where the SPRs are described more fully. Except for the Link Register (LR), the Count Register (CTR), the Fixed-point Exception Register (XER), User SPR General 0 (USPRG0, and read access to SPR General 4–7 (SPRG4–SPRG7), all SPRs are privileged.
Page 36: Count Register (Ctr)
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table 2-1. PPC405 SPRs Function Register Access Page Configuration CCR0 Privileged User Branch Control User DAC1 DAC2 Privileged DBCR0 DBCR1 Privileged DBSR Privileged Debug DVC1 DVC2 Privileged IAC1 IAC2...
Page 37: Link Register (Lr)
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 2.3.2.2 Link Register (LR) The LR is written from a GPR using mtspr, and by branch instructions that have the LK bit set to 1. Such branch instructions load the LR with the address of the instruction following the branch instruction. Thus, the LR contents can be used as the return address for a subroutine that was called using the branch.
Page 38: Figure 2-6. Fixed Point Exception Register (Xer)
; written by Table 2-2 and Table 2-3 list the PPC405 instructions that update the XER. In the tables, the syntax “[o]” indicates that the instruction has an “o” form that updates XER[SO,OV], and a “non-o” form. The syntax “[.]” indicates that the instruction has a “record”...
Page 39: Special Purpose Registers (Usprg0 And Sprg0-Sprg7)
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 2.3.2.4 Special Purpose Registers (USPRG0 and SPRG0–SPRG7) USPRG0 and SPRG0–SPRG7 are provided for general purpose software use. For example, these registers are used as temporary storage locations. For example, an interrupt handler might save the contents of a GPR to an SPRG, and later restore the GPR from it.
Page 40: Cr Fields After Compare Instructions
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual If a CR field is set by a compare instruction, the bits are set as described in the next section. The CR is part of the user programming model.
Page 41: The Time Base
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual The CR[CR0]LT, GT, EQ subfields are set as the result of an algebraic comparison of the instruction result to 0, regardless of the type of instruction that sets CR[CR0]. If the instruction result is 0, the EQ subfield is set to 1. If the result is not 0, either LT or GT is set, depending on the value of the most significant bit of the result.
Page 42: Machine State Register (Msr)
Figure 2-10 shows the byte, halfword, and word data types and their bit and byte definitions for big endian representations of values. Note that PowerPC bit numbering is reversed from industry conventions; bit 0 represents the most significant bit of a value. Figure 2-10. PPC405 Data Types Word Byte...
Page 43: Alignment For Storage Reference And Cache Control Instructions
An address not divisible by two is misaligned with respect to halfword instructions. The PPC405 implementation handles misalignments within and across word boundaries, but there is a performance penalty because additional cycles are required.
Page 44: Byte Ordering
Preliminary User’s Manual 2.5 Byte Ordering The following discussion describes the “endianness” of the PPC405 core, which, by default and in normal use is “big endian.” The PPC405 also contains “little endian” peripherals and supports the attachment of external little endian peripherals.
Page 45: Big Endian Mapping
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual C structure mapping rules permit the use of padding (skipped bytes) to align scalars on desirable boundaries. The structure mapping examples show each scalar aligned at its natural boundary. This alignment introduces padding of four bytes between a and b, one byte between d and e, and two bytes between e and f.
Page 46: Endian (E) Storage Attribute
SLER controls the endianness of a memory region. Bytes in storage that are accessed as little endian are arranged in true little endian format. The PPC405 does not support the little endian mode defined in the PowerPC architecture and used in PPC401xx and PPC403xx processors.
Page 47: Accessing Data In Little Endian Storage Regions
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual If a storage region is reprogrammed from one endian format to the other, the storage region must be reloaded with program and data structures in the appropriate endian format. If the endian format of instruction memory changes, the ICU must be made coherent with the updates.
Page 48: Figure 2-11. Normal Word Load Or Store (Big Endian Storage Region)
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Figure 2-11. Normal Word Load or Store (Big Endian Storage Region) Memory 0x00 0x01 0x02 0x03 Note that the results are identical to the results of a load/store with byte-reverse in a little endian storage region, as illustrated in Figure 2-12.
Page 49: Instruction Processing
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Note that the results are identical to the results of a normal load/store in a little endian storage region, as illustrated in Figure 2-14. Figure 2-14. Normal Word Load or Store (Little Endian Storage Region)
Page 50: Branch Processing
PFB0 Dispatch 2.7 Branch Processing The PPC405, which provides a variety of conditional and unconditional branching instructions, uses the branch prediction techniques described in Branch Prediction on page 52. 2.7.1 Unconditional Branch Target Addressing Options The unconditional branches (b, ba, bl, bla) carry the displacement to the branch target address as a signed 26-bit value (the 24-bit LI field right-extended with 0b00).
Page 51: Conditional Branch Condition Register Testing
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 2.7.3 Conditional Branch Condition Register Testing Conditional branch instructions can test a CR bit. The value of the BI field specifies the bit to be tested (bit 0–31). The BO field controls whether the CR bit is tested, as described in the following section.
Page 52: Branch Prediction
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table 2-9 lists specific BO field contents, and the resulting actions; z represents a mandatory value of 0, and y is a branch prediction option discussed in Branch Prediction on page 52.
Page 53: Speculative Accesses
There is a considerable performance penalty for fetching from guarded storage, so guarding should be used only when required. Note that, following any reset, the PPC405 operates with all of storage guarded. Note that when address translation is enabled, attempts to fetch from guarded storage result in instruction storage exceptions.
Page 54: Prefetch Distance Down An Unresolved Branch Path
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 2.8.1.1 Prefetch Distance Down an Unresolved Branch Path The fetcher will speculatively access up to 19 instructions down a predicted branch path, whether taken or sequential, regardless of cachability.
Page 55: Fetching Past Tw Or Twi Instructions
SGR consumes 128MB of the address space. Table 2-10 shows two address regions of the PPC405. Suppose a system designer can map all I/O devices and all ROM and SRAM devices into any location in either region. The choices made by the designer can prevent speculative accesses to the memory-mapped I/O devices.
Page 56: Summary
Attempting to execute a privileged instruction while in user mode causes a privileged violation program exception (see Program Interrupt on page 123). The PPC405 does not execute the instruction, and the program counter is loaded with EVPR[0:15] || 0x0700, the address of an exception processing routine.
Page 57: Privileged Sprs
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table 2-11. Privileged Instructions dcbi dccci dcread iccci icread mfdcr mfmsr mfspr For all SPRs except CTR, LR, SPRG4–SPRG7, and XER. See “Privileged SPRs” on page 57 mtdcr mtmsr mtspr For all SPRs except CTR, LR, XER.
Page 58: Privileged Dcrs
Machine Check interrupt after the context synchronizing operation occurs and additional instructions have completed. For the PPC405, this can only occur with Data Machine Check exceptions, and not Instruction Machine Check exceptions.
Page 59 There is no guarantee which XYZ instruction will execute; either the old version or the new (stored) version might. 2. Consider the following instruction sequence, which assumes that the PPC405 uses DCRs to provide bus region control:...
Page 60: Execution Synchronization
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual isync guarantees that all subsequent instructions are fetched and executed using the context established by all previous instructions. isync is a context synchronizing operation; isync causes all subsequently prefetched instructions to be discarded and refetched.
Page 61: Implemented Instruction Set Summary
The PPC405 implements both sync and eieio identically, in the manner described above for sync. In the PowerPC Architecture, sync can function across all processors in a multiprocessor environment; eieio functions only within its executing processor.
Page 62: Instructions Specific To The Powerpc Embedded Environment
2.11.2 Storage Reference Instructions Table 2-14 lists the PPC405 storage reference instructions. Load/store instructions transfer data between memory and the GPRs. These instructions operate on bytes, halfwords, and words. Storage reference instructions also support loading or storing multiple registers, character strings, and bytereversed data.
Page 63: Arithmetic Instructions
Fixed Point Exception Register (XER) on page 37 for more information. Table 2-15 lists the PPC405 arithmetic instructions. In the table, the syntax [o] indicates that an instruction has an “o” form that updates XER[SO,OV], and a “non-o” form. The syntax [.] indicates that the instruction has a “record”...
Page 64: Logical Instructions
See Branch Processing on page 50 for more information on branch operations. Table 2-19 lists the PPC405 branch instructions. In the table, the syntax [l] indicates that the instruction has a “link update” form that updates LR with the address of the instruction after the branch, and a “non-link update” form. The syntax [a] indicates that the instruction has an “absolute address”...
Page 65: Cr Logical Instructions
These instructions rotate operands stored in the GPRs. Rotate instructions can also mask rotated operands. Table 2-21 lists the PPC405 rotate instructions. In the table, the syntax [.] indicates that the instruction has a “record” form that updates CR[CR0], and a “non-record” form.
Page 66: Cache Management Instructions
The TLB management instructions read and write entries of the TLB array in the MMU, search the TLB array for an entry which will translate a given address, and invalidate all TLB entries. There is also an instruction for synchronizing TLB updates with other processors, but because the PPC405 is for use in uniprocessor environments, this instruction performs no operation.
Page 67: Processor Control Instructions
2.11.9 Processor Control Instructions These instructions move data between the GPRs and SPRs, the CR, and DCRs in the PPC405, and provide traps, system calls, and synchronization controls. Table 2-26 lists the processor management instructions in the PPC405.
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Page 69: Cache Operations
Preliminary User’s Manual 3. Cache Operations The PPC405 incorporates two internal caches, a 16-KB instruction cache and a 16-KB data cache. Instructions and data can be accessed in the caches much faster than in main memory. The instruction cache unit (ICU) controls instruction accesses to main memory and stores frequently used instructions to reduce the overhead of instruction transfers between the instruction pipeline and external memory.
Page 70: Figure 3-1. Instruction Flow
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual As shown in Table 3-1, tag ways A and B store instruction address bits A0:21 for each line in cache ways A and B. Instruction address bits A19:26 serve as the index to the cache array. The two cache lines that correspond to the same line index (one in each way) are called a congruence class.
Page 71: Icu Operations
The performance of the PPC405 is significantly lower while fetching instructions from cache inhibited regions. Following system reset, address translation is disabled and all ICCR bits are reset to 0 so that no memory regions are cacheable.
Page 72: Icu Coherency
Programming Note: To prevent the occurrence of cache synonyms, use only page sizes greater than the cache way size (8KB), if possible. For the PPC405, the minimum such page size is 16KB. 3.3.4 ICU Coherency The ICU does not “snoop” external memory or the DCU. Programmers must follow special procedures for ICU synchronization when self-modifying code is used or if a peripheral device updates memory containing instructions.
Page 73: Dcu Operations
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table 3-2. Data Cache Organization Tags (Two-way Set) Data (Two-way Set) Way A Way B Way A Way B Line 0 A Line 0 B Line 0 A Line 0 B...
Page 74: Dcu Write Strategies
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Cache lines are always completely flushed or filled, even if the program does not request the rest of the bytes in the line, or if a bus error occurs after a bus interface unit accepts the request for the line fill. If a bus error occurs during a line fill, the line is filled and the data is marked valid.
Page 75: Data Cachability Control
The PowerPC Architecture does not support memory models in which write-through is enabled and caching is inhibited. The performance of the PPC405 is significantly lower while accessing memory in cache-inhibited regions. Following system reset, address translation is disabled and all DCCR bits are reset to 0 so that no memory regions are cacheable.
Page 76: Dcu Instructions
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual icbi Instruction Cache Block Invalidate Invalidates a cache block. icbt Instruction Cache Block Touch Initiates a block fill, enabling a program to begin a cache block fetch before the program needs an instruction in the block.
Page 77: Cache Control And Debugging Features
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual dcbt Data Cache Block Touch Fills a block with data, if the address is cacheable and the data is not already in the cache. If the address is non cacheable, this instruction is a no-op.
Page 78 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 10:11 ICU PLB Priority Bits 0:1 00 Lowest ICU PLB priority 01 Next to lowest ICU PLB priority 10 Next to highest ICU PLB priority 11 Highest ICU PLB priority...
Page 79: Ccr0 Programming Guidelines
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 3.6.1 CCR0 Programming Guidelines Several fields in CCR0 affect ICU and DCU operation. Altering these fields while the cache units are involved in PLB transfers can cause errant operation, including a processor hang.
Page 80: Icu Debugging
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual In the following sample code, registers RN, RM, RX, and RZ are any available GPRs. !SEQUENCE 2 Alter CCR0[DPP1, U0XE) ! Turn off interrupts mfmsr addis RZ,r0,0x0002 ! CE bit...
Page 81: Dcu Debugging
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 3.6.3 DCU Debugging dcread instruction provides a debugging tool for reading the data cache entries for the congruence class specified by EA18:26. The cache information is read into a GPR.
Page 82: Cache Operation Priorities
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual The DCU can accept up to three outstanding store commands before stalling the CPU pipeline for additional data cache commands. The DCU can have two flushes pending before stalling the CPU pipeline.
Page 83 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Sequential line fills can limit DCU performance. Line fills occur when a load/store or dcbt instruction misses in the cache, and can be pipelined on the PLB interface such that up to two requests can be accepted before stalling subsequent requests.
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Page 85: On-Chip Memory (Ocm)
PLB interface. The system designer must ensure that each address has a single access path into the PPC405 CPU for a given software process. Each address that is requested should be found in either the OCM address space or the PLB address space, but not in both.
Page 86: Ocm Addressing
64MB address space, or each can have its own 64MB address space. The address spaces are fully relocatable on 64MB boundaries within the 4GB address space of the PPC405, but the programmer must assign OCM address space to avoid conflicts with other assigned addresses. See Programming Model on page 31 for information about the PPC405 memory map.
Page 87: Table 4-1. Examples Of Store Data Bypass
16KB address representation for the load and store operations, not the 4KB address (the physical size of the PPC405 OCM array). If the 16KB address compares, the store data is bypassed to the load operation. This implies that a bypass results for address aliasing only when the OCM addresses match at a 16KB multiple, which corresponds to a match of address bits 18:29 (a word address that is further specified by byte enables).
Page 88: Ocm Registers
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Examples 5 and 6 bypass data out of the store data queue because the aliased addresses compare within a 16KB address space. In both examples, address bits 18:29 match, and load data is returned from the store data queue.
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Page 91: Memory Management
The MMU translates EAs into real addresses; the instruction cache unit (ICU) and data cache unit (DCU) use real addresses to access memory. The PPC405 MMU supports demand-paged virtual memory and other memory management schemes that depend on precise control of effective to real address mapping and flexible memory protection. Translation misses and protection faults cause precise interrupts.
Page 92: Translation Lookaside Buffer (Tlb)
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Figure 5-1. Effective-to-Real Address Translation Flow 32-bit EA PID Register [0:n–1] [n:31] Effective Page Address Offset [0:23] [24:31] [0:7] [8:n 8:39] 40-bit Virtual Address Effective Page Address Offset Unified TLB 64-entry Fully-associative Array [0:n–1]...
Page 93: Tlb Fields
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Figure 5-2. TLB Entries (Process ID) TLBHI (Tag entry) 26 27 E U0 SIZE TLBLO (Data entry) 21 22 29 3 031 EX WR ZSEL W I M G The virtual address space is extended by adding an 8-bit translation ID (TID) loaded from the Process ID (PID) register during a TLB access.
Page 94: Translation Field
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table 5-1. TLB Fields Related to Page Size Page Size SIZE Field Bits Compared EPN to EA Comparison RPN Bits Set to 0 0:21 ↔ EA 0:21 — 0:19 ↔ EA 0:19 20:21 0:17 ↔...
Page 95: Access Control Fields
M (memory coherent,1 bit) For implementations that support multiprocessing, the M storage attribute improves the performance of memory coherency management. Because the PPC405 does not provide multi-processor support or hardware support for data coherency, the M bit is implemented, but has no effect.
Page 96: Shadow Instruction Tlb
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual G (guarded,1 bit) When set (TLBLO_entry[G] = 1), indicates that the hardware cannot speculatively access the location for pre- fetching or out-of-order load access. The G storage attribute is typically used to protect memory-mapped I/O from inadvertent access.
Page 97: Shadow Data Tlb
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 5.3.4 Shadow Data TLB To enhance performance, eight data-side TLB entries are kept in a eight-entry fully-associative shadow array. This array, called the data TLB (DTLB), helps to avoid TLB contention between instruction accesses to the TLB and load/store operations.
Page 98: Figure 5-3. Itlb/Dtlb/Utlb Address Resolution
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Figure 5-3. ITLB/DTLB/UTLB Address Resolution Generate I-side Generate D-side Effective Address Effective Address Translation Disabled Translation Enabled Translation Enabled Translation Disabled (MSR[IR]=0) (MSR[IR] = 1) (MSR[DR] = 1) (MSR[DR] = 0)
Page 99: Tlb-Related Interrupts
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 5.4 TLB-Related Interrupts The processor relies on interrupt handling software to implement paged virtual memory, and to enforce protection of specified memory pages. When an interrupt occurs, the processor clears MSR[IR, DR]. Therefore, at the start of all interrupt handlers, the processor operates in real mode for instruction accesses and data accesses.
Page 100: Data Tlb Miss Interrupt
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual • In the supervisor state – Instruction fetch from an EA having TLB_entry[EX] = 0 and ZPR[Z ] other than 11 or 10. – Instruction fetch from an EA having TLB_entry[G] = 1.
Page 101: Tlb Read/Write Instructions (Tlbre/Tlbwe)
System software must also maintain records for this purpose. The PPC405 does not provide hardware reference or change bits, but TLB miss interrupts and data storage interrupts enable system software to maintain reference information for TLB entries and their associated pages, respectively.
Page 102: Access Protection
Preliminary User’s Manual 5.7 Access Protection The PPC405 provides virtual-mode access protection. The TLB entry enables system software to control general access for programs in the problem state, and control write and execute permissions for all pages. The TLB entry can specify zone protection that can override the other access control mechanisms supported in the TLB entries.
Page 103: Zone Protection
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Zone protection can alter write protection (see “Zone Protection” on page 103). In addition, only zone protection can prevent read access of a page defined by a TLB entry.
Page 104: Access Protection For Cache Control Instructions
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 26:27 See the description of Z0. 28:29 See the description of Z0. 30:31 See the description of Z0. Setting ZPR[Zn] = 00 for a ZPR field is the only way to deny read access to a page defined by an otherwise valid TLB entry.
Page 105: Access Protection For String Instructions
No storage attribute control register is implemented for the M storage attribute because the PPC405 does not provide multi-processor support or hardware support for data coherency. These SPRs, called storage attribute control registers, control the various storage attributes when address translation is disabled.
Page 106: Storage Attribute Control Registers
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual The storage attribute control registers divide the 4GB real address space into thirty-two 128MB regions. In a storage attribute control register, bit 0 controls the lowest addressed 128MB region, bit 1 the next higher- addressed 128MB region, and so on.
Page 107: Instruction Cache Cachability Register (Iccr)
The SGR controls the G storage attribute for instruction and data accesses. This attribute does not affect data accesses; the PPC405 does not perform speculative loads or stores. After any reset, all SGR bits are set to 1, marking all storage as guarded. For best performance, system software should clear the guarded attribute of appropriate regions as soon as possible.
Page 108 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual AMCC Proprietary...
Page 109: Interrupt Handling
Table 6-2 on page 113 lists the interrupts handled by the PPC405 in the order of interrupt vector offsets. Detailed descriptions of each interrupt follow, in the same order. Table 6-2 also provides an index to the descriptions.
Page 110: Behavior Of The Ppc405 Implementation
In the PPC405, machine checks are handled as critical interrupts (see Critical and Noncritical Interrupts on page 112). If a machine check is associated with an instruction fetch, the critical interrupt save/restore register contains the address of the instruction being fetched when the machine check occurred.
Page 111: Interrupt Handling Priorities
6.3 Interrupt Handling Priorities The PPC405 processor handles only one interrupt at a time. Multiple simultaneous interrupts are handled in the priority order shown in Table 6-1 (assuming, of course, that the interrupt types are enabled). Multiple interrupts can exist simultaneously, each of which requires the generation of an interrupt.
Page 112: Critical And Noncritical Interrupts
(most synchronous interrupts) or the next sequential instruction to be processed (asynchronous interrupts and system call). If the PPC405 was executing a multicycle instruction (multiply, divide, or cache operation), the instruction is terminated and its address is written in SRR0.
Page 113: Table 6-2. Interrupt Vector Offsets
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Save/Restore Register 1 (SRR1) is written with the contents of the MSR; the MSR is then updated to reflect the new machine context. The new MSR contents take effect beginning with the first instruction of the interrupt handling routine.
Page 114: General Interrupt Handling Registers
6.5.1 Machine State Register (MSR) The MSR is a 32-bit register that holds the current context of the PPC405. When a noncritical interrupt is taken, the MSR contents are written to SRR1; when a critical interrupt is taken, the MSR contents are written to SRR3. When an rfi or rfci instruction executes, the contents of the MSR are read from SRR1 or SRR3, respectively.
Page 115: Save/Restore Registers 0 And 1 (Srr0-Srr1)
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Data Relocate 0 Data address translation is disabled. 1 Data address translation is enabled. 28:31 Reserved 6.5.2 Save/Restore Registers 0 and 1 (SRR0–SRR1) SRR0 and SRR1 are 32-bit registers that hold the interrupted machine context when a noncritical interrupt is processed.
Page 116: Exception Vector Prefix Register (Evpr)
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Figure 6-5. Save/Restore Register 3 (SRR3) 0:31 SRR3 receives a copy of the MSR when a critical interrupt is taken; the MSR is restored from SRR3 rfci when executes.
Page 117: Table 6-3. Esr Alteration By Various Interrupts
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Program interrupt—illegal 0 Illegal Instruction error did not occur. 1 Illegal Instruction error occurred. Program interrupt—privileged 0 Privileged instruction error did not occur. 1 Privileged instruction error occurred. Program interrupt—trap 0 Trap with successful compare did not occur.
Page 118: Data Exception Address Register (Dear)
See Watchdog Timer Interrupt on page 126. After detecting a critical interrupt, if no synchronous precise interrupts are outstanding, the PPC405 immediately takes the critical interrupt and writes the address of the next instruction to be executed in SRR2. Simultaneously, the contents of the MSR are saved in SRR3.
Page 119: Instruction Machine Check Handling
When an instruction-side machine check interrupt occurs, the PPC405 stores the address of the excepting instruction in SRR2. When a data-side machine check occurs, the PPC405 stores the address of the next sequential instruction in SRR2. Simultaneously, for all machine check interrupts, the contents of the MSR are loaded into SRR3.
Page 120: Data Machine Check Handling
TLB miss interrupts are associated with the execution of instruction cache operations. When a data storage interrupt is detected, the PPC405 suppresses the instruction causing the interrupt and writes the instruction address in SRR0. The Data Exception Address Register (DEAR) is loaded with the data address that caused the access violation.
Page 121: Instruction Storage Interrupt
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table 6-7. Register Settings during Data Storage Interrupts SRR0 Written with the EA of the instruction causing the data storage interrupt SRR1 Written with the value of the MSR at the time of the interrupt...
Page 122: External Interrupt
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table 6-8. Register Settings during Instruction Storage Interrupts SRR0 Set to the EA of the instruction for which execute access was not permitted SRR1 Set to the value of the MSR at the time of the interrupt EVPR[0:15] || 0x0400 DIZ ←...
Page 123: Alignment Interrupt
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 6.11 Alignment Interrupt Alignment interrupts are caused by dcbz instructions to non cacheable or write-through storage and misaligned dcread, lwarx, or stwx. instructions. Table 6-10 summarizes the instructions and conditions causing alignment interrupts.
Page 124: System Call Interrupt
Excepting instruction is a trap The program interrupt handler does not need to reset the ESR. When one of the following occurs, the PPC405 does not execute the instruction, but writes the address of the excepting instruction into SRR0: • Attempted execution of a privileged instruction in problem state •...
Page 125: Programmable Interval Timer (Pit) Interrupt
PIT. Time-out is detected when, at the beginning of a clock cycle, TSR[PIS] = 1. (This occurs on the cycle after the PIT decrements on a PIT count of 1.) The PPC405 immediately takes the interrupt. The address of the next sequential instruction is saved in SRR0;...
Page 126: Watchdog Timer Interrupt
FIS ← 1 6.16 Watchdog Timer Interrupt For a general description of the PPC405 timer facilities, see Timer Facilities on page 129 The watchdog timer (WDT) is described in Watchdog Timer on page 133. If the WDT interrupt is enabled by TCR[WIE] and MSR[CE], the PPC405 initiates a WDT interrupt after detecting the first WDT time-out.
Page 127: Data Tlb Miss Interrupt
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 6.17 Data TLB Miss Interrupt The data TLB miss interrupt is generated if data translation is enabled and a valid TLB entry matching the EA and PID is not present. The address of the instruction generating the untranslatable effective data address is saved in SRR0.
Page 128: Debug Interrupt
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 6.19 Debug Interrupt Debug interrupts can be either synchronous or asynchronous. These debug events generate synchronous interrupts: branch taken (BT), data address compare (DAC), data value compare (DVC), instruction address compare (IAC), instruction completion (IC), and trap instruction (TIE).
Page 129: Timer Facilities
Preliminary User’s Manual 7. Timer Facilities The PPC405 processor core provides four timer facilities: a time base, a Programmable Interval Timer (PIT), a fixed interval timer (FIT), and a watchdog timer. The PIT is a Special Purpose Register (SPR). These facilities, which are driven by the same base clock, can, among other things, be used for: •...
Page 130: Time Base
Preliminary User’s Manual 7.1 Time Base The PowerPC Architecture The PPC405 implements a 64-bit time base as required in . The time base, which increments once during each period of the source clock, provides a time reference. Read access to the time base is through the mftb instruction. mftb provides user-mode read-only access to the time base.
Page 131: Reading The Time Base
PPC405 Processor Revision 1.01 - February 19, 2007 Preliminary User’s Manual 7.1.1 Reading the Time Base The following code provides an example of reading the time base. mftb moves the low-order 32 bits of the time base to a GPR; mftbu moves the high-order 32 bits of the time base to a second GPR.
Page 132: Fixed Interval Timer (Fit)
PPC405 Processor Revision 1.01 - February 19, 2007 Preliminary User’s Manual 1. Write a 0 to TCR[PIE]. This prevents PIT activity from causing interrupts. 2. Write a 0 to TCR[ARE]. This disables the PIT auto-reload feature. 3. Write zeroes to the PIT to halt PIT decrementing. Although this action does not cause a pit PIT interrupt to become pending, a near-simultaneous decrement to 0 might have done so.
Page 133: Watchdog Timer
PPC405 Processor Revision 1.01 - February 19, 2007 Preliminary User’s Manual 7.3 Watchdog Timer The watchdog timer aids system recovery from software or hardware faults. A watchdog timeout occurs on 0→1 transitions of a selected bit from the time base, as shown in Table 7-3.
Page 134: Table 7-4. Watchdog Timer State Machine
PPC405 Processor Revision 1.01 - February 19, 2007 Preliminary User’s Manual Table 7-4. Watchdog Timer State Machine Watchdog Timer Enable Next Watchdog Status Action When Timer Interval Expires TSR[ENW] TSR[WIS] Set TSR[ENW] = 1. Set TSR[ENW] = 1. Set TSR[WIS] = 1.
Page 135: Timer Status Register (Tsr)
PPC405 Processor Revision 1.01 - February 19, 2007 Preliminary User’s Manual 7.4 Timer Status Register (TSR) The TSR can be accessed for read or write-to-clear. Status registers are generally set by hardware and read and cleared by software. The mfspr instruction reads the TSR.
Page 136: Figure 7-7. Timer Control Register (Tcr)
PPC405 Processor Revision 1.01 - February 19, 2007 Preliminary User’s Manual Figure 7-7. Timer Control Register (TCR) Watchdog Period 00 2 clocks 01 2 clocks 10 2 clocks 11 2 clocks Watchdog Reset Control TCR[WRC] resets to 00. 00 No Watchdog reset will occur.
Page 137: Debugging
The PPC405 provides JTAG and trace interfaces to support hardware and software test and debug. Typically, the JTAG interface connects to a debug port external to the PPC405; the debug port is typically connected to a JTAG connector on a processor board.
Page 138: Jtag Connector
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 8.3.1 JTAG Connector A 16-pin male 2x8 header connector is suggested as the JTAG debug port connector. This connector definition RISCWatch matches the requirements of the RISCWatch debugger. The connector is described in detail in Debugger User’s Guide...
Page 139: Jtag Implementation
8.5 Debug Modes The PPC405 supports the following debug modes, each of which supports a type of debug tool or debug task commonly used in embedded systems development: • Internal debug mode, which supports ROM monitors •...
Page 140: Internal Debug Mode
DBCR0[EDM] = 1 and MSR[DE] = 1. 8.5.3 Debug Wait Mode In debug wait mode, debug events cause the PPC405 to enter a state in which interrupts can be serviced while the processor appears to be stopped.
Page 141: Real-Time Trace Debug Mode
For example, while the PPC405 is in debug wait mode, an external device might generate an interrupt that requires immediate service. The PPC405 can service the interrupt (vector to an interrupt handler and execute the interrupt handler code) and return to the previous stopped state.
Page 142: Processor Control
Revision 1.02 - September 10, 2007 Preliminary User’s Manual 8.6 Processor Control The PPC405 provides the following debug functions for processor control. Not all facilities are available in all debug modes. Instruction Step The processor is stepped one instruction at a time, while stopped, using the JTAG debug port.
Page 143: Debug Control Registers
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 8.8.1 Debug Control Registers The debug control registers (DBCR0 and DBCR1)can enable and configure debug events, reset the processor, control timer operation during debug events, enable debug interrupts, and set the processor debug mode.
Page 144: Debug Control Register 1 (Dbcr1)
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Instruction Address Exclusive Range Compare 3–4: Selects range defined by IAC3 and IAC4 to be 0 Inclusive IA34X inclusive or exclusive. 1 Exclusive Instruction Address Range Compare 1-2 Toggle:...
Page 145: Debug Status Register (Dbsr)
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Type of data comparison used: Data Value Compare 1 Mode: 00 Undefined All bytes selected by DBCR1[DV1BE] must com- 01 AND pare to the appropriate bytes of DVC1. One of the bytes selected by DBCR1[DV1BE] must...
Page 146 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Trap Instruction Debug Event: 0 Event did not occur 1 Event occurred Unconditional Debug Event: 0 Event did not occur 1 Event occurred IAC1 Debug Event: 0 Event did not occur...
Page 147: Instruction Address Compare Registers (Iac1-Iac4)
8.8.3 Instruction Address Compare Registers (IAC1–IAC4) The PPC405 can take a debug event upon an attempt to execute an instruction from an address. The address, which must be word-aligned, is defined in an IAC register. The DBCR0[IA1, IA2] fields of DBCR0 controls the instruction address compare (IAC) debug event.
Page 148: Instruction Complete Debug Event
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual In internal debug mode, the processor generates a debug interrupt when a debug event occurs. In external debug mode, the processor stops when a debug event occurs. When internal and external debug mode are both enabled, the processor stops on a debug event with the debug interrupt pending.
Page 149: Trap Taken Debug Event
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 8.8.10 Trap Taken Debug Event This debug event occurs before execution of a trap instruction where the conditions are such that the trap will occur. When trap is enabled for a debug event, external debug mode is enabled, internal debug mode is enabled with MSR[DE] enabled, or debug wait mode is enabled, a trap instruction will not cause a program exception.
Page 150: Dac Debug Event
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Figure 8-7. Inclusive IAC Range Address Compares FFFF FFFF IAC1 IAC2 Figure 8-8 shows the range selected in an inclusive IAC range address compare. Note that the address in IAC1 is not considered part of the range, but the address in IAC2 is, along with the highest memory address, as shown in the preceding examples.
Page 151: Dac Range Address Compare
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual DAC 1 Size Byte address 00 Compare all bits 01 Ignore LSB (least significant bit) Halfword address 10 Ignore two LSBs Word address 11 Ignore five LSBs Cache line (...
Page 152: Dac Applied To Cache Instructions
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Figure 8-10. Exclusive DAC Range Address Compares FFFF FFFF DAC1 DAC2 The DAC Compare Size fields (DBCR1[D1S, D2S]) are not used by DAC range comparisons. 8.8.13.3 DAC Applied to Cache Instructions Some cache instructions can cause DAC debug events.
Page 153: Dac Applied To String Instructions
In a debug environment, the fact that external memory is being written is the event of interest. Even though dcread dccci are not address-specific (they affect a congruence class regardless of the instruction operand address), and are considered “loads,” in the PPC405 they do not cause DAC debug events. icbi icbt iccci icread...
Page 154: Table 8-4. Setting Of Dbsr Bits For Dac And Dvc Events
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table 8-4. Setting of DBSR Bits for DAC and DVC Events DBCR1 DBSR DACn Event DVCn Enabled DVCn Event [DnR] [DnW] [DA12] [DRn] [DWn] — — — — —...
Page 155: Imprecise Debug Event
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table 8-6. Comparisons for Aligned DVC Accesses Access DBCR1[DVnBE] Setting Value Operation Word Word value Halfword (Low-Order) Halfword value replicated AND-OR Halfword (High-Order) Halfword value replicated AND-OR Byte Byte value replicated For halfword accesses, the halfword value is replicated in the “empty”...
Page 156 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual AMCC Proprietary...
Page 157: Instruction Set
Programs using these instructions are not portable to PowerPC implementations that do not implement the PowerPC Embedded Environment. The PPC405 implements a number of implementation-specific instructions that are not part of the PowerPC Archi- tecture or the PowerPC Embedded Environment, which are listed in Table 9-1. In the table, the syntax [o] indicates that an instruction has an o form, which updates the XER[SO,OV] fields, and a non-o form.
Page 158: Pseudocode
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Instruction bits 0 through 5 always contain the primary opcode. Many instructions have an extended opcode in another field. The remaining instruction bits contain additional fields. All instruction fields belong to one of the following categories: •...
Page 159 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual A hexadecimal number A binary number An instruction or register field A bit in a named instruction or register field A range of bits in a named instruction or register field A list of bits, by number or name, in a named instruction or register field b,b, .
Page 160: Operator Precedence
Condition Register (CR) and the Fixed-point Exception Register (XER). For discussion of the CR, see Condi- tion Register (CR) on page 39. For discussion of XER, see Fixed Point Exception Register (XER) on page 37. 9.5 Alphabetical Instruction Listing The following pages list the instructions available in the PPC405 in alphabetical order. AMCC Proprietary...
Page 161 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual RT, RA, RB OE= 0, Rc= 0 add. RT, RA, RB OE= 0, Rc= 1 addo RT, RA, RB OE= 1, Rc= 0 addo. RT, RA, RB OE= 1, Rc= 1 21 22 ←...
Page 162 PPC405 Processor Revision 1.02 - September 10, 2007 addc Preliminary User’s Manual Add Carrying addc Add Carrying addc RT, RA, RB OE= 0, Rc= 0 addc. RT, RA, RB OE= 0, Rc= 1 addco RT, RA, RB OE= 1, Rc= 0 addco.
Page 163 PPC405 Processor Revision 1.02 - September 10, 2007 adde Preliminary User’s Manual Add Extended adde Add Extended adde RT, RA, RB OE= 0, Rc= 0 adde. RT, RA, RB OE= 0, Rc= 1 addeo RT, RA, RB OE= 1, Rc= 0 addeo.
Page 164: Table 9-3. Extended Mnemonics For Addi
PPC405 Processor Revision 1.02 - September 10, 2007 addi Preliminary User’s Manual Add Immediate addi Add Immediate addi RT, RA, IM ← (RT) (RA|0) + EXTS(IM) If the RA field is 0, the IM field, sign-extended to 32 bits, is placed into register RT.
Page 165: Table 9-4. Extended Mnemonics For Addic
PPC405 Processor Revision 1.02 - September 10, 2007 addic Preliminary User’s Manual Add Immediate Carrying addic Add Immediate Carrying addic RT, RA, IM ← (RT) (RA) + EXTS(IM) if (RA) + EXTS(IM) – 1 then > ← XER[CA] else ←...
Page 166: Table 9-5. Extended Mnemonics For Addic
PPC405 Processor Revision 1.02 - September 10, 2007 addic. Preliminary User’s Manual Add Immediate Carrying and Record addic. Add Immediate Carrying and Record addic. RT, RA, IM ← (RT) (RA) + EXTS(IM) if (RA) + EXTS(IM) – 1 then >...
Page 167: Table 9-6. Extended Mnemonics For Addis
PPC405 Processor Revision 1.02 - September 10, 2007 addis Preliminary User’s Manual Add Immediate Shifted addis Add Immediate Shifted addis RT, RA, IM ← (RT) (RA|0) + (IM If the RA field is 0, the IM field is concatenated on its right with sixteen 0-bits and placed into register RT.
Page 168 PPC405 Processor Revision 1.02 - September 10, 2007 addme Preliminary User’s Manual Add to Minus One Extended addme Add to Minus One Extended addme RT, RA OE= 0, Rc= 0 addme. RT, RA OE= 0, Rc= 1 addmeo RT, RA OE=1, Rc= 0 addmeo.
Page 169 PPC405 Processor Revision 1.02 - September 10, 2007 addze Preliminary User’s Manual Add to Zero Extended addze Add to Zero Extended addze RT, RA OE=0, Rc=0 addze. RT, RA OE=0, Rc=1 addzeo RT, RA OE=1, Rc=0 addzeo. RT, RA OE=1, Rc=1 21 22 ←...
Page 170 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual RA, RS, RB Rc=0 and. RA, RS, RB Rc=1 ← ∧ (RA) (RS) (RB) The contents of register RS are ANDed with the contents of register RB; the result is placed into register RA.
Page 171 PPC405 Processor Revision 1.02 - September 10, 2007 andc Preliminary User’s Manual AND with Complement andc AND with Complement andc RA,RS,RB Rc=0 andc. RA,RS,RB Rc=1 21 2 ← ∧ ¬ (RA) (RS) (RB) The contents of register RS are ANDed with the ones complement of the contents of register RB; the result is placed into register RA.
Page 172 PPC405 Processor Revision 1.02 - September 10, 2007 andi. Preliminary User’s Manual AND Immediate andi. AND Immediate andi. RA, RS, IM ← ∧ (RA) (RS) The IM field is extended to 32 bits by concatenating 16 0-bits on its left. The contents of register RS is ANDed with the extended IM field;...
Page 173 PPC405 Processor Revision 1.02 - September 10, 2007 andis. Preliminary User’s Manual AND Immediate Shifted andis. AND Immediate Shifted andis. RA, RS, IM ← ∧ (RA) (RS) The IM field is extended to 32 bits by concatenating 16 0-bits on its right. The contents of register RS are ANDed with the extended IM field;...
Page 174 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Branch Branch target AA=0, LK=0 target AA=1, LK=0 target AA=0, LK=1 target AA=1, LK=1 AA LK 30 31 If AA = 1 then ← target 6:29 ← EXTS(LI else ←...
Page 175 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Branch Conditional Branch Conditional BO, BI, target AA=0, LK= 0 BO, BI, target AA =1, LK= 0 BO, BI, target AA= 0, LK=1 bcla BO, BI, target AA =1, LK=1...
Page 176: Table 9-7. Extended Mnemonics For Bc, Bca, Bcl, Bcla
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Branch Conditional Architecture Note This instruction is part of the PowerPC User Instruction Set Architecture. Table 9-7. Extended Mnemonics for bc, bca, bcl, bcla Other Registers Mnemonic Operands Function Altered Decrement CTR;...
Page 177 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Branch Conditional Table 9-7. Extended Mnemonics for bc, bca, bcl, bcla (Continued) Other Registers Mnemonic Operands Function Altered Decrement CTR Branch if CTR = 0 AND CR = 0.
Page 178 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Branch Conditional Table 9-7. Extended Mnemonics for bc, bca, bcl, bcla (Continued) Other Registers Mnemonic Operands Function Altered Branch if greater than or equal. Use CR0 if cr_field is omitted.
Page 179 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Branch Conditional Table 9-7. Extended Mnemonics for bc, bca, bcl, bcla (Continued) Other Registers Mnemonic Operands Function Altered Branch if not equal. Use CR0 if cr_field is omitted. Extended mnemonic for bc 4,4∗cr_field+2,target...
Page 180 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Branch Conditional Table 9-7. Extended Mnemonics for bc, bca, bcl, bcla (Continued) Other Registers Mnemonic Operands Function Altered Branch if not unordered. Use CR0 if cr_field is omitted. Extended mnemonic for bc 4,4∗cr_field+3,target...
Page 181: Table 9-8. Extended Mnemonics For Bcctr, Bcctrl
PPC405 Processor Revision 1.02 - September 10, 2007 bcctr Preliminary User’s Manual Branch Conditional to Count Register bcctr Branch Conditional to Count Register bcctr BO, BI LK = 0 bcctrl BO, BI LK =1 if BO = 0 then ←...
Page 182 PPC405 Processor Revision 1.02 - September 10, 2007 bcctr Preliminary User’s Manual Branch Conditional to Count Register Table 9-8. Extended Mnemonics for bcctr, bcctrl (Continued) Other Registers Mnemonic Operands Function Altered [cr_field] Branch, if equal, to address in CTR Use CR0 if cr_field is omitted.
Page 183 PPC405 Processor Revision 1.02 - September 10, 2007 bcctr Preliminary User’s Manual Branch Conditional to Count Register Table 9-8. Extended Mnemonics for bcctr, bcctrl (Continued) Other Registers Mnemonic Operands Function Altered [cr_field] Branch, if not less than, to address in CTR.
Page 184: Table 9-9. Extended Mnemonics For Bclr, Bclrl
PPC405 Processor Revision 1.02 - September 10, 2007 bclr Preliminary User’s Manual Branch Conditional to Link Register bclr Branch Conditional to Link Register bclr BO, BI LK = 0 bclrl BO, BI LK =1 if BO = 0 then ←...
Page 185 PPC405 Processor Revision 1.02 - September 10, 2007 bclr Preliminary User’s Manual Branch Conditional to Link Register Table 9-9. Extended Mnemonics for bclr, bclrl (Continued) Other Registers Mnemonic Operands Function Altered Decrement CTR. Branch if CTR ≠ 0 to address in LR.
Page 186 PPC405 Processor Revision 1.02 - September 10, 2007 bclr Preliminary User’s Manual Branch Conditional to Link Register Table 9-9. Extended Mnemonics for bclr, bclrl (Continued) Other Registers Mnemonic Operands Function Altered Branch, if greater than or equal, to address in LR.
Page 187 PPC405 Processor Revision 1.02 - September 10, 2007 bclr Preliminary User’s Manual Branch Conditional to Link Register Table 9-9. Extended Mnemonics for bclr, bclrl (Continued) Other Registers Mnemonic Operands Function Altered Branch if not unordered to address in LR. Use CR0 if cr_field is omitted.
Page 188: Table 9-10. Extended Mnemonics For Cmp
The PowerPC Architecture defines this instruction as cmp BF,L,RA,RB, where L selects operand size for 64-bit PowerPC implementations. For all 32-bit PowerPC implementations, L = 0 is required (L = 1 is an invalid form); hence for PPC405, use of the extended mnemonic cmpw BF,RA,RB is recommended. Architecture Note This instruction is part of the PowerPC User Instruction Set Architecture.
Page 189: Table 9-11. Extended Mnemonics For Cmpi
The PowerPC Architecture defines this instruction as cmpi BF,L,RA,IM, where L selects operand size for 64-bit PowerPC implementations. For all 32-bit PowerPC implementations, L = 0 is required (L = 1 is an invalid form); hence for the PPC405, use of the extended mnemonic cmpwi BF,RA,IM is recommended. Architecture Note This instruction is part of the PowerPC User Instruction Set Architecture.
Page 190: Table 9-12. Extended Mnemonics For Cmpl
The PowerPC Architecture defines this instruction as cmpl BF,L,RA,RB, where L selects operand size for 64-bit PowerPC implementations. For all 32-bit PowerPC implementations, L = 0 is required (L = 1 is an invalid form); hence for PPC405, use of the extended mnemonic cmplw BF,RA,RB is recommended. Architecture Note This instruction is part of the PowerPC User Instruction Set Architecture.
Page 191: Table 9-13. Extended Mnemonics For Cmpli
The PowerPC Architecture defines this instruction as cmpli BF,L,RA,IM, where L selects operand size for 64-bit PowerPC implementations. For all 32-bit PowerPC implementations, L = 0 is required (L = 1 is an invalid form); hence for the PPC405, use of the extended mnemonic cmplwi BF,RA,IM is recommended. Architecture Note This instruction is part of the PowerPC User Instruction Set Architecture.
Page 192 PPC405 Processor Revision 1.02 - September 10, 2007 cntlzw Preliminary User’s Manual Count Leading Zeros Word cntlzw Count Leading Zeros Word cntlzw RA, RS Rc=0 cntlzw. RA, RS Rc=1 ← do while n < 32 if (RS) = 1 then leave ←...
Page 193 PPC405 Processor Revision 1.02 - September 10, 2007 crand Preliminary User’s Manual Condition Register AND crand Condition Register AND crand BT, BA, BB ← ∧ The CR bit specified by the BA field is ANDed with the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field.
Page 194 PPC405 Processor Revision 1.02 - September 10, 2007 crandc Preliminary User’s Manual Condition Register AND with Complement crandc Condition Register AND with Complement crandc BT, BA, BB ← ∧ ¬ The CR bit specified by the BA field is ANDed with the ones complement of the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field.
Page 195: Table 9-14. Extended Mnemonics For Creqv
PPC405 Processor Revision 1.02 - September 10, 2007 creqv Preliminary User’s Manual Condition Register Equivalent creqv Condition Register Equivalent creqv BT, BA, BB ← ¬ ⊕ The CR bit specified by the BA field is XORed with the CR bit specified by the BB field; the ones complement of the result is placed into the CR bit specified by the BT field.
Page 196 PPC405 Processor Revision 1.02 - September 10, 2007 crnand Preliminary User’s Manual Condition Register NAND crnand Condition Register NAND crnand BT, BA, BB ← ¬ ∧ The CR bit specified by the BA field is ANDed with the CR bit specified by the BB field; the ones complement of the result is placed into the CR bit specified by the BT field.
Page 197: Table 9-15. Extended Mnemonics For Crnor
PPC405 Processor Revision 1.02 - September 10, 2007 crnor Preliminary User’s Manual Condition Register NOR crnor Condition Register NOR crnor BT, BA, BB ← ¬ ∨ The CR bit specified by the BA field is ORed with the CR bit specified by the BB field; the ones complement of the result is placed into the CR bit specified by the BT field.
Page 198: Table 9-16. Extended Mnemonics For Cror
PPC405 Processor Revision 1.02 - September 10, 2007 cror Preliminary User’s Manual Condition Register OR cror Condition Register OR cror BT, BA, BB ← ∨ The CR bit specified by the BA field is ORed with the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field.
Page 199 PPC405 Processor Revision 1.02 - September 10, 2007 crorc Preliminary User’s Manual Condition Register OR with Complement crorc Condition Register OR with Complement crorc BT, BA, BB ← ∨ ¬ The condition register (CR) bit specified by the BA field is ORed with the ones complement of the CR bit specified by the BB field;...
Page 200: Table 9-17. Extended Mnemonics For Crxor
PPC405 Processor Revision 1.02 - September 10, 2007 crxor Preliminary User’s Manual Condition Register XOR crxor Condition Register XOR crxor BT, BA, BB ← ⊕ The CR bit specified by the BA field is XORed with the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field.
Page 201 If the data block at the EA is not in the data cache and marked as write-through, architecturally the instruction can establish a cache block and set the block to 0, or a no-op can occur. For the PPC405, a no-op occurs.
Page 202 PPC405 Processor Revision 1.02 - September 10, 2007 dcba Preliminary User’s Manual Data Cache Block Allocate This instruction is considered a “store” with respect to data address compare (DAC) debug exceptions. See Data Storage Interrupt on page 120. Architecture Note This instruction is part of the PowerPC Embedded Virtual Environment.
Page 203 PPC405 Processor Revision 1.02 - September 10, 2007 dcbf Preliminary User’s Manual Data Cache Block Flush dcbf Data Cache Block Flush dcbf RA, RB ← (RA|0) + (RB) DCBF(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 204 PPC405 Processor Revision 1.02 - September 10, 2007 dcbi Preliminary User’s Manual Data Cache Block Invalidate dcbi Data Cache Block Invalidate dcbi RA, RB ← (RA|0) + (RB) DCBI(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 205 PPC405 Processor Revision 1.02 - September 10, 2007 dcbst Preliminary User’s Manual Data Cache Block Store dcbst Data Cache Block Store dcbst RA, RB ← (RA|0) + (RB) DCBST(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 206 PPC405 Processor Revision 1.02 - September 10, 2007 dcbt Preliminary User’s Manual Data Cache Block Touch dcbt Data Cache Block Touch dcbt RA, RB ← (RA|0) + (RB) DCBT(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 207 PPC405 Processor Revision 1.02 - September 10, 2007 dcbtst Preliminary User’s Manual Data Cache Block Touch for Store dcbtst Data Cache Block Touch for Store dcbtst RA, RB ← (RA|0) + (RB) DCBTST(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 208 PPC405 Processor Revision 1.02 - September 10, 2007 dcbz Preliminary User’s Manual Data Cache Block Set to Zero dcbz Data Cache Block Set to Zero dcbz RA, RB 1014 ← (RA|0) + (RB) DCBZ(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 209 PPC405 Processor Revision 1.02 - September 10, 2007 dcbz Preliminary User’s Manual Data Cache Block Set to Zero This instruction is considered a “store” with respect to data address compare (DAC) debug exceptions. See Debug Interrupt on page 128. Architecture Note This instruction is part of the PowerPC Embedded Virtual Environment.
Page 210 PPC405 Processor Revision 1.02 - September 10, 2007 dccci Preliminary User’s Manual Data Cache Congruence Class Invalidate dccci Data Cache Congruence Class Invalidate dccci RA, RB ← (RA|0) + (RB) DCCCI(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 211 PPC405 Processor Revision 1.02 - September 10, 2007 dcread Preliminary User’s Manual Data Cache Read dcread Data Cache Read dcread RT, RA, RB ← (RA|0) + (RB) ∧ ← if ((CCR0[CIS] = 0) (CCR0[CWS] = 0)) then (RT) (d-cache data, way A) ∧...
Page 212 PPC405 Processor Revision 1.02 - September 10, 2007 dcread Preliminary User’s Manual Data Cache Read Exceptions If EA is not word-aligned, an alignment exception occurs. This instruction is considered a “load” with respect to data storage exceptions, but cannot cause a data storage exception.
Page 213 PPC405 Processor Revision 1.02 - September 10, 2007 divw Preliminary User’s Manual Divide Word divw Divide Word divw RT, RA, RB OE=0, Rc=0 divw. RT, RA, RB OE=0, Rc=1 divwo RT, RA, RB OE=1, Rc=0 divwo. RT, RA, RB OE=1, Rc=1 21 22 ←...
Page 214 PPC405 Processor Revision 1.02 - September 10, 2007 divwu Preliminary User’s Manual Divide Word Unsigned divwu Divide Word Unsigned divwu RT, RA, RB OE=0, Rc=0 divwu. RT, RA, RB OE=0, Rc=1 divwuo RT, RA, RB OE=1, Rc=0 divwuo. RT, RA, RB...
Page 215 Architecturally, eieio orders storage access, not instruction completion. Therefore, non-storage operations after eieio could complete before storage operations that were before eieio. The sync instruction guarantees ordering of both instruction completion and storage access. For the PPC405, the eieio instruction is implemented to behave as a sync instruction.
Page 216 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Equivalent Equivalent RA, RS, RB Rc=0 eqv. RA, RS, RB Rc=1 (RA) ← ¬((RS) ⊕ (RB)) The contents of register RS are XORed with the contents of register RB; the ones complement of the result is placed into register RA.
Page 217 PPC405 Processor Revision 1.02 - September 10, 2007 extsb Preliminary User’s Manual Extend Sign Byte extsb Extend Sign Byte extsb RA, RS Rc=0 extsb. RA, RS Rc=1 ← (RA) EXTS(RS) 24:31 The least significant byte of register RS is sign-extended to 32 bits by replicating bit 24 of the register into bits 0 through 23 of the result.
Page 218 PPC405 Processor Revision 1.02 - September 10, 2007 extsh Preliminary User’s Manual Extend Sign Halfword extsh Extend Sign Halfword extsh RA, RS Rc=0 extsh. RA, RS Rc=1 ← (RA) EXTS(RS) 16:31 The least significant halfword of register RS is sign-extended to 32 bits by replicating bit 16 of the register into bits 0 through 15 of the result.
Page 219 PPC405 Processor Revision 1.02 - September 10, 2007 icbi Preliminary User’s Manual Instruction Cache Block Invalidate 0.Instruction Set icbi Instruction Cache Block Invalidate icbi RA, RB ← 0) + (RB) ICBI(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 220 PPC405 Processor Revision 1.02 - September 10, 2007 icbt Preliminary User’s Manual Instruction Cache Block Touch icbt Instruction Cache Block Touch icbt RA, RB ← (RA|0) + (RB) ICBT(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 221 PPC405 Processor Revision 1.02 - September 10, 2007 iccci Preliminary User’s Manual Instruction Cache Congruence Class Invalidate iccci Instruction Cache Congruence Class Invalidate iccci RA, RB ← (RA|0) + (RB) ICCCI(ICU cache array) This instruction invalidates the entire ICU cache array. The EA is not used; previous implementations have used the EA for protection checks.
Page 222 PPC405 Processor Revision 1.02 - September 10, 2007 icread Preliminary User’s Manual Instruction Cache Read icread Instruction Cache Read icread RA, RB ← (RA|0) + (RB) ∧ ← if ((CCR0[CIS] = 0) (CCR0[CWS] = 0)) then (ICDBDR) (i-cache data, way A) ∧...
Page 223 PPC405 Processor Revision 1.02 - September 10, 2007 icread Preliminary User’s Manual Instruction Cache Read icread r5,r6 # read cache information isync # ensure completion of icread mficdbdr r7 # move information to GPR Instruction cache operations use MSR[DR], not MSR[IR], to determine translation of their operands. When data translation is disabled, cachability for the EA of the operand of instruction cache operations is determined by the ICCR, not the DCCR.
Page 224 PPC405 Processor Revision 1.02 - September 10, 2007 isync Preliminary User’s Manual Instruction Synchronize isync Instruction Synchronize isync The isync instruction is a context synchronizing instruction. isync provides an ordering function for the effects of all instructions executed by the processor. Executing isync insures that all instructions preceding the isync instruction execute before isync completes, except that storage accesses caused by those instructions need not have completed.
Page 225 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Load Byte and Zero Load Byte and Zero RT, D(RA) ← (RA|0) + EXTS(D) ← (RT) 0 || MS(EA,1) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 226 PPC405 Processor Revision 1.02 - September 10, 2007 lbzu Preliminary User’s Manual Load Byte and Zero with Update lbzu Load Byte and Zero with Update lbzu RT, D(RA) ← (RA|0) + EXTS(D) ← (RA) ← (RT) 0 || MS(EA,1) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 227 PPC405 Processor Revision 1.02 - September 10, 2007 lbzux Preliminary User’s Manual Load Byte and Zero with Update Indexed lbzux Load Byte and Zero with Update Indexed lbzux RT, RA, RB ← (RA|0) + (RB) ← (RA) ← (RT) 0 || MS(EA,1) An effective address (EA) is formed by adding an index to a base address.
Page 228 PPC405 Processor Revision 1.02 - September 10, 2007 lbzx Preliminary User’s Manual Load Byte and Zero Indexed lbzx Load Byte and Zero Indexed lbzx RT,RA, RB ← (RA|0) + (RB) ← (RT) 0 || MS(EA,1) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 229 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Load Halfword Algebraic 0.Instruction Set Load Halfword Algebraic RT, D(RA) ← (RA|0) + EXTS(D) ← (RT) EXTS(MS(EA,2)) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 230 PPC405 Processor Revision 1.02 - September 10, 2007 lhau Preliminary User’s Manual Load Halfword Algebraic with Update lhau Load Halfword Algebraic with Update lhau RT, D(RA) ← (RA) + EXTS(D) ← (RA) ← (RT) EXTS(MS(EA,2)) An effective address (EA) is formed by adding a displacement to the base address in register RA. The displace- ment is obtained by sign-extending the 16-bit D field to 32 bits.
Page 231 PPC405 Processor Revision 1.02 - September 10, 2007 lhaux Preliminary User’s Manual Load Halfword Algebraic with Update Indexed lhaux Load Halfword Algebraic with Update Indexed lhaux RT, RA, RB ← (RA) + (RB) ← (RA) ← (RT) EXTS(MS(EA,2)) An effective address (EA) is formed by adding an index to the base address in register RA. The index is the contents of register RB.
Page 232 PPC405 Processor Revision 1.02 - September 10, 2007 lhax Preliminary User’s Manual Load Halfword Algebraic Indexed lhax Load Halfword Algebraic Indexed lhax RT, RA, RB ← (RA|0) + (RB) ← (RT) EXTS(MS(EA,2)) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 233 PPC405 Processor Revision 1.02 - September 10, 2007 lhbrx Preliminary User’s Manual Load Halfword Byte-Reverse Indexed lhbrx Load Halfword Byte-Reverse Indexed hbrx RT, RA, RB ← (RA|0) + (RB) ← (RT) 0 || MS(EA +1,1) || MS(EA,1) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 234 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Load Halfword and Zero Load Halfword and Zero RT, D(RA) ← (RA|0) + EXTS(D) ← (RT) 0 || MS(EA,2) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 235 PPC405 Processor Revision 1.02 - September 10, 2007 lhzu Preliminary User’s Manual Load Halfword and Zero with Update lhzu Load Halfword and Zero with Update lhzu RT, D(RA) ← (RA) + EXTS(D) ← (RA) ← (RT) 0 || MS(EA,2) An effective address (EA) is formed by adding a displacement to the base address in register RA. The displace- ment is obtained by sign-extending the 16-bit D field to 32 bits.
Page 236 PPC405 Processor Revision 1.02 - September 10, 2007 lhzux Preliminary User’s Manual Load Halfword and Zero with Update Indexed lhzux Load Halfword and Zero with Update Indexed hzux RT, RA, RB ← (RA) + (RB) ← (RA) ← (RT) 0 || MS(EA,2) An effective address (EA) is formed by adding an index to the base address in register RA.
Page 237 PPC405 Processor Revision 1.02 - September 10, 2007 lhzx Preliminary User’s Manual Load Halfword and Zero Indexed lhzx Load Halfword and Zero Indexed lhzx RT, RA, RB ← (RA|0) + (RB) ← (RT) 0 || MS(EA,2) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 238 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Load Multiple Word Load Multiple Word RT, D(RA) ← (RA|0) + EXTS(D) ← ≤ do while r ≠ ∨ if ((r (r = 31)) then ← (GPR(r)) MS(EA,4) ←...
Page 239 PPC405 Processor Revision 1.02 - September 10, 2007 lswi Preliminary User’s Manual Load String Word Immediate lswi Load String Word Immediate RT, RA, NB ← (RA|0) if NB = 0 then ← else ← ← ← ((RT + CEIL(CNT/4) – 1) % 32) FINAL ←...
Page 240 PPC405 Processor Revision 1.02 - September 10, 2007 lswi Preliminary User’s Manual Load String Word Immediate Invalid Instruction Forms • Reserved fields • RA is in the range of registers to be loaded • RA = RT = 0 Architecture Note This instruction is part of the PowerPC User Instruction Set Architecture.
Page 241 PPC405 Processor Revision 1.02 - September 10, 2007 lswx Preliminary User’s Manual Load String Word Indexed lswx Load String Word Indexed lswx RT, RA, RB ← (RA|0) + (RB) ← XER[TBC] ← ← ((RT + CEIL(CNT/4) – 1) % 32) FINAL ←...
Page 242 However, the PowerPC Architecture makes no statement regarding imprecise exceptions related to lswx with XER[TBC] = 0. The PPC405 generates an imprecise exception (machine check) on this instruction when all of the following conditions are true: •...
Page 243 PPC405 Processor Revision 1.02 - September 10, 2007 lwarx Preliminary User’s Manual Load Word and Reserve Indexed lwarx Load Word and Reserve Indexed warx RT, RA, RB ← (RA|0) + (RB) ← RESERVE ← (RT) MS(EA,4) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 244 PPC405 Processor Revision 1.02 - September 10, 2007 lwbrx Preliminary User’s Manual Load Word Byte-Reverse Indexed lwbrx Load Word Byte-Reverse Indexed lwbrx RT, RA, RB ← (RA|0) + (RB) ← (RT) MS(EA+3,1) MS(EA+2,1) MS(EA+1,1) MS(EA,1) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 245 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Load Word and Zero Load Word and Zero RT, D(RA) ← (RA|0) + EXTS(D) ← (RT) MS(EA,4) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 246 PPC405 Processor Revision 1.02 - September 10, 2007 lwzu Preliminary User’s Manual Load Word and Zero with Update lwzu Load Word and Zero with Update lwzu RT, D(RA) ← (RA) + EXTS(D) ← (RA) ← (RT) MS(EA,4) An effective address (EA) is formed by adding a displacement to the base address in register RA. The displace- ment is obtained by sign-extending the 16-bit D field to 32 bits.
Page 247 PPC405 Processor Revision 1.02 - September 10, 2007 lwzux Preliminary User’s Manual Load Word and Zero with Update Indexed lwzux Load Word and Zero with Update Indexed lwzux RT, RA, RB ← (RA) + (RB) ← (RA) ← (RT) MS(EA,4) An effective address (EA) is formed by adding an index to the base address in register RA.
Page 248 PPC405 Processor Revision 1.02 - September 10, 2007 lwzx Preliminary User’s Manual Load Word and Zero Indexed lwzx Load Word and Zero Indexed lwzx RT, RA, RB ← (RA|0) + (RB) ← (RT) MS(EA,4) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 249 PPC405 Processor Revision 1.02 - September 10, 2007 macchw Preliminary User’s Manual Multiply Accumulate Cross Halfword to Word Modulo Signed macchw Multiply Accumulate Cross Halfword to Word Modulo Signed macchw RT, RA, RB OE=0, Rc=0 macchw. RT, RA, RB OE=0, Rc=1...
Page 250 PPC405 Processor Revision 1.02 - September 10, 2007 macchws Preliminary User’s Manual Multiply Accumulate Cross Halfword to Word Saturate Signed macchws Multiply Accumulate Cross Halfword to Word Saturate Signed macchws RT, RA, RB OE=0, Rc=0 macchws. RT, RA, RB OE=0, Rc=1...
Page 251 PPC405 Processor Revision 1.02 - September 10, 2007 macchwsu Preliminary User’s Manual Multiply Accumulate Cross Halfword to Word Saturate Unsigned macchwsu Multiply Accumulate Cross Halfword to Word Saturate Unsigned macchwsu RT, RA, RB OE=0, Rc=0 macchwsu. RT, RA, RB OE=0, Rc=1...
Page 252 PPC405 Processor Revision 1.02 - September 10, 2007 macchwu Preliminary User’s Manual Multiply Accumulate Cross Halfword to Word Modulo Unsigned macchwu Multiply Accumulate Cross Halfword to Word Modulo Unsigned macchwu RT, RA, RB OE=0, Rc=0 macchwu. RT, RA, RB OE=0, Rc=1...
Page 253 PPC405 Processor Revision 1.02 - September 10, 2007 machhw Preliminary User’s Manual Multiply Accumulate High Halfword to Word Modulo Signed machhw Multiply Accumulate High Halfword to Word Modulo Signed machhw RT, RA, RB OE=0, Rc=0 machhw. RT, RA, RB OE=0, Rc=1...
Page 254 PPC405 Processor Revision 1.02 - September 10, 2007 machhws Preliminary User’s Manual Multiply Accumulate High Halfword to Word Saturate Signed machhws Multiply Accumulate High Halfword to Word Saturate Signed machhws RT, RA, RB OE=0, Rc=0 machhws. RT, RA, RB OE=0, Rc=1...
Page 255 PPC405 Processor Revision 1.02 - September 10, 2007 machhwsu Preliminary User’s Manual Multiply Accumulate High Halfword to Word Saturate Unsigned machhwsu Multiply Accumulate High Halfword to Word Saturate Unsigned machhwsu RT, RA, RB OE=0, Rc=0 machhwsu. RT, RA, RB OE=0, Rc=1...
Page 256 PPC405 Processor Revision 1.02 - September 10, 2007 machhwu Preliminary User’s Manual Multiply Accumulate High Halfword to Word Modulo Unsigned machhwu Multiply Accumulate High Halfword to Word Modulo Unsigned machhwu RT, RA, RB OE=0, Rc=0 machhwu. RT, RA, RB OE=0, Rc=1...
Page 257 PPC405 Processor Revision 1.02 - September 10, 2007 maclhw Preliminary User’s Manual Multiply Accumulate Low Halfword to Word Modulo Signed maclhw Multiply Accumulate Low Halfword to Word Modulo Signed maclhw RT, RA, RB OE=0, Rc=0 maclhw. RT, RA, RB OE=0, Rc=1...
Page 258 PPC405 Processor Revision 1.02 - September 10, 2007 maclhws Preliminary User’s Manual Multiply Accumulate Low Halfword to Word Saturate Signed maclhws Multiply Accumulate Low Halfword to Word Saturate Signed maclhws RT, RA, RB OE=0, Rc=0 maclhws. RT, RA, RB OE=0, Rc=1...
Page 259 PPC405 Processor Revision 1.02 - September 10, 2007 maclhwsu Preliminary User’s Manual Multiply Accumulate Low Halfword to Word Saturate Unsigned maclhwsu Multiply Accumulate Low Halfword to Word Saturate Unsigned maclhwsu RT, RA, RB OE=0, Rc=0 maclhwsu. RT, RA, RB OE=0, Rc=1...
Page 260 PPC405 Processor Revision 1.02 - September 10, 2007 maclhwu Preliminary User’s Manual Multiply Accumulate Low Halfword to Word Modulo Unsigned maclhwu Multiply Accumulate Low Halfword to Word Modulo Unsigned maclhwu RT, RA, RB OE=0, Rc=0 maclhwu. RT, RA, RB OE=0, Rc=1...
Page 261 PPC405 Processor Revision 1.02 - September 10, 2007 mcrf Preliminary User’s Manual Move Condition Register Field mcrf Move Condition Register Field mcrf BF, BFA ← ← ← (CR[CRn]) (CR[CRm]) The contents of the CR field specified by the BFA field are placed into the CR field specified by the BF field.
Page 262: Table 9-18. Transfer Bit Mnemonic Assignment
PPC405 Processor Revision 1.02 - September 10, 2007 mcrxr Preliminary User’s Manual Move to Condition Register from XER 25.Instruction Set mcrxr Move to Condition Register from XER mcrxr ← ← (CR[CRn]) ← The contents of XER are placed into the CR field specified by the BF field. XER are then set to 0.
Page 263 PPC405 Processor Revision 1.02 - September 10, 2007 mfcr Preliminary User’s Manual Move From Condition Register mfcr Move From Condition Register mfcr ← (RT) (CR) The contents of the CR are placed into register RT. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Page 264 PPC405 Processor Revision 1.02 - September 10, 2007 mfdcr Preliminary User’s Manual Move from Device Control Register mfdcr Move from Device Control Register mfdcr RT, DCRN DCRF ← DCRN DCRF DCRF ← (RT) (DCR(DCRN)) The contents of the DCR specified by the DCRF field are placed into register RT.
Page 265 PPC405 Processor Revision 1.02 - September 10, 2007 mfmsr Preliminary User’s Manual Move From Machine State Register 25.Instruction Set mfmsr Move From Machine State Register mfmsr ← (RT) (MSR) The contents of the MSR are placed into register RT. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Page 266 PPC405 Processor Revision 1.02 - September 10, 2007 mfspr Preliminary User’s Manual Move From Special Purpose Register mfspr Move From Special Purpose Register mfspr RT, SPRN SPRF ← SPRN SPRF SPRF ← (RT) (SPR(SPRN)) The contents of the SPR specified by the SPRF field are placed into register RT. See Special Purpose Registers on page 354 for a listing of SPR mnemonics and corresponding SPRN and SPRF values.
Page 267: Table 9-19. Extended Mnemonics For Mfspr
PPC405 Processor Revision 1.02 - September 10, 2007 mfspr Preliminary User’s Manual Move From Special Purpose Register Table 9-19. Extended Mnemonics for mfspr Other Mnemonic Operands Function Registers Changed mfccr0 mfctr mfdac1 mfdac2 mfdear mfdbcr0 mfdbcr1 mfdbsr mfdccr mfdcwr mfdvc1...
Page 268: Table 9-20. Extended Mnemonics For Mftb
PPC405 Processor Revision 1.02 - September 10, 2007 mftb Preliminary User’s Manual Move From Time Base mftb Move From Time Base mftb RT, TBRN TBRF ← TBRN TBRF TBRF ← (RT) (TBR(TBRN)) The contents of the time base register (TBR) specified by the TBRF field are placed into register RT. The following table lists the TBRN and TBRF values.
Page 269: Table 9-22. Extended Mnemonics For Mtcrf
PPC405 Processor Revision 1.02 - September 10, 2007 mtcrf Preliminary User’s Manual Move to Condition Register Fields mtcrf Move to Condition Register Fields mtcrf FXM, RS 11 12 20 21 ← mask (FXM (FXM (FXM (FXM ← ∧ ∨ ∧ ¬...
Page 270 PPC405 Processor Revision 1.02 - September 10, 2007 mtdcr Preliminary User’s Manual Move To Device Control Register mtdcr Move To Device Control Register mtdcr DCRN, RS DCRF ← DCRN DCRF || DCRF ← (DCR(DCRN)) (RS) The contents of register RS are placed into the DCR specified by the DCRF field.
Page 271 PPC405 Processor Revision 1.02 - September 10, 2007 mtmsr Preliminary User’s Manual Move To Machine State Register 25.Instruction Set mtmsr Move To Machine State Register mtmsr ← (MSR) (RS) The contents of register RS are placed into the MSR. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Page 272 PPC405 Processor Revision 1.02 - September 10, 2007 mtspr Preliminary User’s Manual Move To Special Purpose Register mtspr Move To Special Purpose Register mtspr SPRN, RS SPRF ← SPRN SPRF SPRF ← (SPR(SPRN)) (RS) The contents of register RS are placed into register RT. See Special Purpose Registers on page 354 for a listing of SPR mnemonics and corresponding SPRN and SPRF values.
Page 273: Table 9-23. Extended Mnemonics For Mtspr
PPC405 Processor Revision 1.02 - September 10, 2007 mtspr Preliminary User’s Manual Move To Special Purpose Register Table 9-23. Extended Mnemonics for mtspr Other Registers Mnemonic Operands Function Altered mtccr0 mtctr mtdac1 mtdac2 mtdbcr0 mtdbcr1 mtdbsr mtdccr mtdcwr mtdear mtdvc1...
Page 274 PPC405 Processor Revision 1.02 - September 10, 2007 mulchw Preliminary User’s Manual Multiply Cross Halfword to Word Signed 25.Instruction Set mulchw Multiply Cross Halfword to Word Signed mulchw RT, RA, RB Rc=0 mulchw. RT, RA, RB Rc=1 ← (RT) (RA)
Page 275 PPC405 Processor Revision 1.02 - September 10, 2007 mulchwu Preliminary User’s Manual Multiply Cross Halfword to Word Unsigned mulchwu Multiply Cross Halfword to Word Unsigned mulchwu RT, RA, RB Rc=0 mulchwu. RT, RA, RB Rc=1 ← (RT) (RA) x (RB)
Page 276 PPC405 Processor Revision 1.02 - September 10, 2007 mulhhw Preliminary User’s Manual Multiply High Halfword to Word Signed mulhhw Multiply High Halfword to Word Signed mulhhw RT, RA, RB Rc=0 mulhhw. RT, RA, RB Rc=1 ← (RT) (RA) x (RB)
Page 277 PPC405 Processor Revision 1.02 - September 10, 2007 mulhhwu Preliminary User’s Manual Multiply High Halfword to Word Unsigned mulhhwu Multiply High Halfword to Word Unsigned mulhhwu RT, RA, RB Rc=0 mulhhwu. RT, RA, RB Rc=1 ← (RT) (RA) x (RB)
Page 278 PPC405 Processor Revision 1.02 - September 10, 2007 mulhw Preliminary User’s Manual Multiply High Word mulhw Multiply High Word mulhw RT, RA, RB Rc=0 mulhw. RT, RA, RB Rc=1 21 22 ← × prod (RA) (RB) signed 0:63 ← (RT)
Page 279 PPC405 Processor Revision 1.02 - September 10, 2007 mulhwu Preliminary User’s Manual Multiply High Word Unsigned mulhwu Multiply High Word Unsigned mulhwu RT, RA, RB Rc=0 mulhwu. RT, RA, RB Rc=1 ← × prod (RA) (RB) unsigned 0:63 ← (RT)
Page 280 PPC405 Processor Revision 1.02 - September 10, 2007 mullhw Preliminary User’s Manual Multiply Low Halfword to Word Signed mullhw Multiply High Halfword to Word Signed mullhw RT, RA, RB Rc=0 mullhw. RT, RA, RB Rc=1 ← (RT) (RA) x (RB)
Page 281 PPC405 Processor Revision 1.02 - September 10, 2007 mullhwu Preliminary User’s Manual Multiply Low Halfword to Word Unsigned mullhwu Multiply High Halfword to Word Unsigned mullhwu RT, RA, RB OE=0, Rc=0 mullhwu. RT, RA, RB OE=0, Rc=1 ← (RT) (RA)
Page 282 PPC405 Processor Revision 1.02 - September 10, 2007 mulli Preliminary User’s Manual Multiply Low Immediate mulli Multiply Low Immediate mulli RT, RA, IM ← × prod (RA) EXTS(IM) signed 0:47 ← (RT) prod 16:47 The 48-bit product of register RA and the sign-extended IM field is formed. Both register RA and the IM field are interpreted as signed quantities.
Page 283 PPC405 Processor Revision 1.02 - September 10, 2007 mullw Preliminary User’s Manual Multiply Low Word mullw Multiply Low Word mullw RT, RA, RB OE=0, Rc=0 mullw. RT, RA, RB OE=0, Rc=1 mullwo RT, RA, RB OE=1, Rc=0 mullwo. RT, RA, RB...
Page 284 PPC405 Processor Revision 1.02 - September 10, 2007 nand Preliminary User’s Manual NAND nand NAND nand RA, RS, RB Rc=0 nand. RA, RS, RB Rc=1 ← ¬ ∧ (RA) ((RS) (RB)) The contents of register RS is ANDed with the contents of register RB; the ones complement of the result is placed into register RA.
Page 285 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Negate Negate RT, RA OE=0, Rc=0 neg. RT, RA OE=0, Rc=1 nego RT, RA OE=1, Rc=0 nego. RT, RA OE=1, Rc=1 21 22 ← ¬ (RT) (RA) + 1 The twos complement of the contents of register RA are placed into register RT.
Page 286 PPC405 Processor Revision 1.02 - September 10, 2007 nmacchw Preliminary User’s Manual Negative Multiply Accumulate Cross Halfword to Word Modulo nmacchw Negative Multiply Accumulate Cross Halfword to Word Modulo Signed nmacchw RT, RA, RB OE=0, Rc=0 nmacchw. RT, RA, RB...
Page 287 PPC405 Processor Revision 1.02 - September 10, 2007 nmacchws Preliminary User’s Manual Negative Multiply Accumulate Cross Halfword to Word Saturate nmacchws Negative Multiply Accumulate High Halfword to Word Saturate Signed nmacchws RT, RA, RB OE=0, Rc=0 nmacchws. RT, RA, RB...
Page 288 PPC405 Processor Revision 1.02 - September 10, 2007 nmachhw Preliminary User’s Manual Negative Multiply Accumulate High Halfword to Word Modulo nmachhw Negative Multiply Accumulate High Halfword to Word Modulo Signed nmachhw RT, RA, RB OE=0, Rc=0 nmachhw. RT, RA, RB...
Page 289 PPC405 Processor Revision 1.02 - September 10, 2007 nmachhws Preliminary User’s Manual Negative Multiply Accumulate High Halfword to Word Saturate nmachhws Negative Multiply Accumulate High Halfword to Word Saturate Signed nmachhws RT, RA, RB OE=0, Rc=0 nmachhws. RT, RA, RB...
Page 290 PPC405 Processor Revision 1.02 - September 10, 2007 nmaclhw Preliminary User’s Manual Negative Multiply Accumulate Low Halfword to Word Modulo Signed nmaclhw Negative Multiply Accumulate Low Halfword to Word Modulo Signed nmaclhw RT, RA, RB OE=0, Rc=0 nmaclhw. RT, RA, RB...
Page 291 PPC405 Processor Revision 1.02 - September 10, 2007 nmaclhws Preliminary User’s Manual Negative Multiply Accumulate High Halfword to Word Saturate nmaclhws Negative Multiply Accumulate Low Halfword to Word Saturate Signed nmaclhws RT, RA, RB OE=0, Rc=0 nmaclhws. RT, RA, RB...
Page 292: Table 9-24. Extended Mnemonics For Nor, Nor
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual RA, RS, RB Rc=0 nor. RA, RS, RB Rc=1 ← ¬ ∨ (RA) ((RS) (RB)) The contents of register RS is ORed with the contents of register RB; the ones complement of the result is placed into register RA.
Page 293: Table 9-25. Extended Mnemonics For Or, Or
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual RA, RS, RB Rc=0 RA, RS, RB Rc=1 ← ∨ (RA) (RS) (RB) The contents of register RS is ORed with the contents of register RB; the result is placed into register RA.
Page 294 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual OR with Complement OR with Complement RA, RS, RB Rc=0 orc. RA, RS, RB Rc=1 ← ∨ ¬ (RA) (RS) (RB) The contents of register RS is ORed with the ones complement of the contents of register RB; the result is placed into register RA.
Page 295: Table 9-26. Extended Mnemonics For Ori
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual OR Immediate OR Immediate RA, RS, IM ← ∨ (RA) (RS) 0 || IM) The IM field is extended to 32 bits by concatenating 16 0-bits on the left. Register RS is ORed with the extended IM field;...
Page 296 PPC405 Processor Revision 1.02 - September 10, 2007 oris Preliminary User’s Manual OR Immediate Shifted oris OR Immediate Shifted oris RA, RS, IM ← ∨ (RA) (RS) The IM Field is extended to 32 bits by concatenating 16 0-bits on the right. Register RS is ORed with the extended IM field and the result is placed into register RA.
Page 297 PPC405 Processor Revision 1.02 - September 10, 2007 rfci Preliminary User’s Manual Return From Critical Interrupt rfci Return From Critical Interrupt rfci ← (PC) (SRR2) ) ← (MSR (SRR3) The program counter (PC) is restored with the contents of SRR2 and the MSR is restored with the contents of SRR3.
Page 298 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Return From Interrupt Return From Interrupt ← (PC) (SRR0) ← (MSR) (SRR1) The program counter (PC) is restored with the contents of SRR0 and the MSR is restored with the contents of SRR1.
Page 299: Table 9-27. Extended Mnemonics For Rlwimi, Rlwimi
PPC405 Processor Revision 1.02 - September 10, 2007 rlwimi Preliminary User’s Manual Rotate Left Word Immediate then Mask Insert rlwimi Rotate Left Word Immediate then Mask Insert rlwimi RA, RS, SH, MB, ME Rc=0 rlwimi. RA, RS, SH, MB, ME Rc=1 ←...
Page 300: Table 9-28. Extended Mnemonics For Rlwinm, Rlwinm
PPC405 Processor Revision 1.02 - September 10, 2007 rlwinm Preliminary User’s Manual Rotate Left Word Immediate then AND with Mask rlwinm Rotate Left Word Immediate then AND with Mask rlwinm RA, RS, SH, MB, ME Rc=0 rlwinm. RA, RS, SH, MB, ME Rc=1 ←...
Page 301 PPC405 Processor Revision 1.02 - September 10, 2007 rlwinm Preliminary User’s Manual Rotate Left Word Immediate then AND with Mask Table 9-28. Extended Mnemonics for rlwinm, rlwinm. (Continued) Other Registers Mnemonic Operands Function Altered Extract and left justify immediate. ( >...
Page 302: Table 9-29. Extended Mnemonics For Rlwnm, Rlwnm
PPC405 Processor Revision 1.02 - September 10, 2007 rlwnm Preliminary User’s Manual Rotate Left Word then AND with Mask rlwnm Rotate Left Word then AND with Mask rlwnm RA, RS, RB, MB, ME Rc=0 rlwnm. RA, RS, RB, MB, ME Rc=1 ←...
Page 303 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual System Call System Call 30 31 ← (SRR1) (MSR) ← (SRR0) (PC) ← EVPR || 0x0C00 0:15 ← (MSR[WE, EE, PR, DR, IR]) A system call exception is generated. The contents of the MSR are copied into SRR1 and (4 + address of sc instruction) is placed into SRR0.
Page 304 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Shift Left Word Shift Left Word RA, RS, RB Rc=0 slw. RA, RS, RB Rc=1 ← (RB) 27:31 ← ROTL((RS), n) if (RB) = 0 then ← MASK(0, 31 – n) else ←...
Page 305 PPC405 Processor Revision 1.02 - September 10, 2007 sraw Preliminary User’s Manual Shift Right Algebraic Word sraw Shift Right Algebraic Word sraw RA, RS, RB Rc=0 sraw. RA, RS, RB Rc=1 ← (RB) 27:31 ← ROTL((RS), 32 – n) if (RB) = 0 then ←...
Page 306 PPC405 Processor Revision 1.02 - September 10, 2007 srawi Preliminary User’s Manual Shift Right Algebraic Word Immediate srawi Shift Right Algebraic Word Immediate srawi RA, RS, SH Rc=0 srawi. RA, RS, SH Rc=1 ← ← ROTL((RS), 32 – n) ←...
Page 307 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Shift Right Word Shift Right Word RA, RS, RB Rc=0 srw. RA, RS, RB Rc=1 ← (RB) 27:31 ← ROTL((RS), 32 – n) if (RB) = 0 then ←...
Page 308 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Store Byte Store Byte RS, D(RA) ← (RA|0) + EXTS(D) ← MS(EA, 1) (RS) 24:31 An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 309 PPC405 Processor Revision 1.02 - September 10, 2007 stbu Preliminary User’s Manual Store Byte with Update stbu Store Byte with Update stbu RS, D(RA) ← (RA) + EXTS(D) ← MS(EA, 1) (RS) 24:31 ← (RA) An effective address (EA) is formed by adding a displacement to the base address in register RA. The displace- ment is obtained by sign-extending the 16-bit D field to 32 bits.
Page 310 PPC405 Processor Revision 1.02 - September 10, 2007 stbux Preliminary User’s Manual Store Byte with Update Indexed stbux Store Byte with Update Indexed stbux RS, RA, RB ← (RA) + (RB) ← MS(EA, 1) (RS) 24:31 ← (RA) An effective address (EA) is formed by adding an index to the base address in register RA. The index is the contents of register RB.
Page 311 PPC405 Processor Revision 1.02 - September 10, 2007 stbx Preliminary User’s Manual Store Byte Indexed stbx Store Byte Indexed stbx RS, RA, RB ← (RA|0) + (RB) ← MS(EA, 1) (RS) 24:31 An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 312 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Store Halfword 25.Instruction Set Store Halfword RS, D(RA) ← (RA|0) + EXTS(D) ← MS(EA, 2) (RS) 16:31 An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 313 PPC405 Processor Revision 1.02 - September 10, 2007 sthbrx Preliminary User’s Manual Store Halfword Byte-Reverse Indexed sthbrx Store Halfword Byte-Reverse Indexed sthbrx RS, RA, RB ← (RA|0) + (RB) ← MS(EA, 2) (RS) (RS) 24:31 16:23 An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 314 PPC405 Processor Revision 1.02 - September 10, 2007 sthu Preliminary User’s Manual Store Halfword with Update sthu Store Halfword with Update sthu RS, D(RA) ← (RA) + EXTS(D) ← MS(EA, 2) (RS) 16:31 ← (RA) An effective address (EA) is formed by adding a displacement to the base address in register RA. The displace- ment is obtained by sign-extending the 16-bit D field to 32 bits.
Page 315 PPC405 Processor Revision 1.02 - September 10, 2007 sthux Preliminary User’s Manual Store Halfword with Update Indexed sthux Store Halfword with Update Indexed sthux RS, RA, RB ← (RA) + (RB) ← MS(EA, 2) (RS) 16:31 ← (RA) An effective address (EA) is formed by adding an index to the base address in register RA. The index is the contents of register RB.
Page 316 PPC405 Processor Revision 1.02 - September 10, 2007 sthx Preliminary User’s Manual Store Halfword Indexed sthx Store Halfword Indexed sthx RS, RA, RB ← (RA|0) + (RB) ← MS(EA, 2) (RS) 16:31 An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 317 PPC405 Processor Revision 1.02 - September 10, 2007 stmw Preliminary User’s Manual Store Multiple Word stmw Store Multiple Word stmw RS, D(RA) ← (RA|0) + EXTS(D) ← ≤ do while r ← MS(EA, 4) (GPR(r)) ← r + 1 ←...
Page 318 PPC405 Processor Revision 1.02 - September 10, 2007 stswi Preliminary User’s Manual Store String Word Immediate stswi Store String Word Immediate stswi RS, RA, NB ← (RA|0) if NB = 0 then ← else ← ← RS – 1 ←...
Page 319 PPC405 Processor Revision 1.02 - September 10, 2007 stswx Preliminary User’s Manual Store String Word Indexed stswx Store String Word Indexed stswx RS, RA, RB ← (RA|0) + (RB) ← XER[TBC] ← RS – 1 ← do while n > 0 if i = 0 then ←...
Page 320 PPC405 Processor Revision 1.02 - September 10, 2007 stswx Preliminary User’s Manual Store String Word Indexed • The address is passed to the data cache • The address misses in the data cache (resulting in a line fill request) • The address encounters some form of bus error (non-configured, for example) Architecture Note This instruction is part of the PowerPC User Instruction Set Architecture.
Page 321 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Store Word Store Word RS, D(RA) ← (RA|0) + EXTS(D) ← MS(EA, 4) (RS) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits.
Page 322 PPC405 Processor Revision 1.02 - September 10, 2007 stwbrx Preliminary User’s Manual Store Word Byte-Reverse Indexed stwbrx Store Word Byte-Reverse Indexed stwbrx RS, RA, RB ← (RA|0) + (RB) ← MS(EA, 4) (RS) (RS) (RS) (RS) 24:31 16:23 8:15 An EA is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
Page 323 PPC405 Processor Revision 1.02 - September 10, 2007 stwcx. Preliminary User’s Manual Store Word Conditional Indexed stwcx. Store Word Conditional Indexed stwcx. RS, RA, RB ← (RA|0) + (RB) if RESERVE = 1 then ← MS(EA, 4) (RS) ← RESERVE ←...
Page 324 PPC405 Processor Revision 1.02 - September 10, 2007 stwu Preliminary User’s Manual Store Word with Update stwu Store Word with Update stwu RS, D(RA) ← (RA) + EXTS(D) ← MS(EA, 4) (RS) ← (RA) An effective address (EA) is formed by adding a displacement to the base address in register RA. The displace- ment is obtained by sign-extending the 16-bit D field to 32 bits.
Page 325 PPC405 Processor Revision 1.02 - September 10, 2007 stwux Preliminary User’s Manual Store Word with Update Indexed stwux Store Word with Update Indexed stwux RS, RA, RB ← (RA) + (RB) ← MS(EA, 4) (RS) ← (RA) An effective address (EA) is formed by adding an index to the base address in register RA. The index is the contents of register RB.
Page 326 PPC405 Processor Revision 1.02 - September 10, 2007 stwx Preliminary User’s Manual Store Word Indexed stwx Store Word Indexed stwx RS, RA, RB ← (RA|0) + (RB) ← MS(EA,4) (RS) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
Page 327: Table 9-30. Extended Mnemonics For Subf, Subf., Subfo, Subfo
PPC405 Processor Revision 1.02 - September 10, 2007 subf Preliminary User’s Manual Subtract From subf Subtract From subf RT, RA, RB OE=0, Rc=0 subf. RT, RA, RB OE=0, Rc=1 subfo RT, RA, RB OE=1, Rc=0 subfo. RT, RA, RB OE=1, Rc=1 21 22 ←...
Page 328: Table 9-31. Extended Mnemonics For Subfc, Subfc., Subfco, Subfco
PPC405 Processor Revision 1.02 - September 10, 2007 subfc Preliminary User’s Manual Subtract From Carrying subfc Subtract From Carrying subfc RT, RA, RB OE=0, Rc=0 subfc. RT, RA, RB OE=0, Rc=1 subfco RT, RA, RB OE=1, Rc=0 subfco. RT, RA, RB...
Page 329 PPC405 Processor Revision 1.02 - September 10, 2007 subfe Preliminary User’s Manual Subtract From Extended subfe Subtract From Extended subfe RT, RA, RB OE=0, Rc=0 subfe. RT, RA, RB OE=0, Rc=1 subfeo RT, RA, RB OE=1, Rc=0 subfeo. RT, RA, RB...
Page 330 PPC405 Processor Revision 1.02 - September 10, 2007 subfic Preliminary User’s Manual Subtract From Immediate Carrying subfic Subtract From Immediate Carrying subfic RT, RA, IM ← ¬ (RT) (RA) + EXTS(IM) + 1 ¬ (RA) + EXTS(IM) + 1 – 1 then >...
Page 331 PPC405 Processor Revision 1.02 - September 10, 2007 subfme Preliminary User’s Manual Subtract from Minus One Extended subfme Subtract from Minus One Extended subfme RT, RA OE=0, Rc=0 subfme. RT, RA OE=0, Rc=1 subfmeo RT, RA OE=1, Rc=0 subfmeo. RT, RA...
Page 332 PPC405 Processor Revision 1.02 - September 10, 2007 subfze Preliminary User’s Manual Subtract from Zero Extended subfze Subtract from Zero Extended subfze RT, RA OE=0, Rc=0 subfze. RT, RA OE=0, Rc=1 subfzeo RT, RA OE=1, Rc=0 subfzeo. RT, RA OE=1, Rc=1 21 22 ←...
Page 333 Architecturally, the eieio instruction orders storage access, not instruction completion. Therefore, non-storage operations that follow eieio could complete before storage operations that precede eieio. The sync instruction guarantees ordering of instruction completion and storage access. For the PPC405, the eieio instruction is imple- mented to behave as a sync instruction.
Page 334 PPC405 Processor Revision 1.02 - September 10, 2007 tlbia Preliminary User’s Manual TLB Invalidate All tlbia TLB Invalidate All tlbia All of the entries in the TLB are invalidated and become unavailable for translation by clearing the valid (V) bit in the TLBHI portion of each TLB entry.
Page 335 PPC405 Processor Revision 1.02 - September 10, 2007 tlbre Preliminary User’s Manual TLB Read Entry tlbre TLB Read Entry tlbre RT, RA, WS if WS ← (RT) TLBLO[(RA 26:31 else ← (RT) TLBHI[(RA 26:31 ← (PID) TID from TLB[(RA 26:31 The contents of the selected TLB entry is placed into register RT (and possibly into PID).
Page 336: Table 9-32. Extended Mnemonics For Tlbre
PPC405 Processor Revision 1.02 - September 10, 2007 tlbre Preliminary User’s Manual TLB Read Entry Architecture Note This instruction part of the PowerPC Embedded Operating Environment. Table 9-32. Extended Mnemonics for tlbre Other Registers Mnemonic Operands Function Altered Load TLBHI portion of the selected TLB entry into RT.
Page 337 PPC405 Processor Revision 1.02 - September 10, 2007 tlbsx Preliminary User’s Manual TLB Search Indexed tlbsx TLB Search Indexed tlbsx RT, RA, RB Rc=0 tlbsx. RT, RA, RB Rc=1 ← (RA|0) + (RB) if Rc = 1 ← CR[CR0] ←...
Page 338 The tlbsync instruction is provided in the PowerPC architecture to support synchronization of TLB operations among the processors of a multi-processor system. In the PPC405, this instruction performs no operation, and is provided to facilitate code portability. Registers Altered •...
Page 339 PPC405 Processor Revision 1.02 - September 10, 2007 tlbwe Preliminary User’s Manual TLB Write Entry tlbwe TLB Write Entry tlbwe RS, RA, WS if WS ← TLBLO[(RA (RS) 26:31 else ← TLBHI[(RA (RS) 26:31 ← TID of TLB[(RA (PID 26:31 24:31 The contents of the selected TLB entry is replaced with the contents of register RS (and possibly PID).
Page 340: Table 9-33. Extended Mnemonics For Tlbwe
PPC405 Processor Revision 1.02 - September 10, 2007 tlbwe Preliminary User’s Manual TLB Write Entry Architecture Note This instruction part of the PowerPC Embedded Operating Environment. Table 9-33. Extended Mnemonics for tlbwe Other Registers Mnemonic Operands Function Altered Write TLBHI portion of the selected TLB entry from RS.
Page 341 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Trap Word Trap Word TO, RA, RB ∧ = 1) ∨ if ( ((RA) (RB) < ∧ = 1) ∨ ((RA) (RB) > ∧ = 1) ∨ ((RA) (RB) ∧...
Page 342: Table 9-34. Extended Mnemonics For Tw
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Trap Word If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • None Invalid Instruction Forms • Reserved fields Programming Note This instruction is inserted into the execution stream by a debugger to implement breakpoints, and is not typically used by application code.
Page 343 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Trap Word Table 9-34. Extended Mnemonics for tw (Continued) Other Registers Mnemonic Operands Function Altered Trap if (RA) less than (RB). Extended mnemonic for twlt RA, RB tw 16,RA,RB Trap if (RA) not equal to (RB).
Page 344 0:15 • If TRAP is enabled as an External debug event (DBCR[TDE] = 1 and DBCR[EDM] = 1): TRAP goes to the Debug Stop state, to be handled by an external debugger with hardware control of the PPC405. ← (DBSR[TIE])
Page 345: Table 9-35. Extended Mnemonics For Twi
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Trap Word Immediate Registers Altered • None Programming Note This instruction is inserted into the execution stream by a debugger to implement breakpoints, and is not typically used by application code.
Page 346 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Trap Word Immediate Table 9-35. Extended Mnemonics for twi (Continued) Other Registers Mnemonic Operands Function Altered Trap if (RA) not less than EXTS(IM). Extended mnemonic for twnli RA, IM...
Page 347 PPC405 Processor Revision 1.02 - September 10, 2007 wrtee Preliminary User’s Manual Write External Enable wrtee Write External Enable wrtee ← MSR[EE] (RS) The MSR[EE] is set to the value specified by bit 16 of register RS. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Page 348 PPC405 Processor Revision 1.02 - September 10, 2007 wrteei Preliminary User’s Manual Write External Enable Immediate wrteei Write External Enable Immediate wrteei 16 17 ← MSR[EE] MSR[EE] is set to the value specified by the E field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Page 349 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual RA, RS, RB Rc=0 xor. RA, RS, RB Rc=1 ← ⊕ (RA) (RS) (RB) The contents of register RS are XORed with the contents of register RB; the result is placed into register RA.
Page 350 PPC405 Processor Revision 1.02 - September 10, 2007 xori Preliminary User’s Manual XOR Immediate xori XOR Immediate xori RA, RS, IM ← ⊕ (RA) (RS) 0 || IM) The IM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents of register RS are XORed with the extended IM field;...
Page 351 PPC405 Processor Revision 1.02 - September 10, 2007 xoris Preliminary User’s Manual XOR Immediate Shifted xoris XOR Immediate Shifted xoris RA, RS, IM ← ⊕ (RA) (RS) (IM || The IM field is extended to 32 bits by concatenating 16 0-bits on the right. The contents of register RS are XORed with the extended IM field;...
Page 352 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual AMCC Proprietary...
Page 353: Register Summary
Purpose Registers (SPRs), Time Base Registers (TBRs), the Machine State Register (MSR), the Condition Register (CR), Device Control Registers (DCRs), and memory-mapped I/O (MMIO) registers. This chapter provides an alphabetical listing and bit definitiions for all the registers provided by the PPC405 processor.
Page 354: Special Purpose Registers
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual 10.5 Special Purpose Registers Special Purpose Registers (SPRs), which are part of the PowerPC Embedded Environment, are accessed using mtspr mfspr instructions. SPRs control the use of the debug facilities, timers, interrupts, storage control attributes, and other architected processor resources.
Page 355: Time Base Registers
The PowerPC Architecture provides a 64-bit time base. Timer Facilities on page 129 describes the architected time base. In the PPC405, the time base is implemented as two 32-bit time base registers (TBRs). The low-order 32 bits of the time base are read from the TBL and the high-order 32 bits are read from the TBL.
Page 356: Device Control Registers
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table 10-4. Time Base Registers TBRN Mnemonic Register Name TBRF Access Decimal Time Base Lower (Read-only) 0x10C 0x188 Read-only Time Base Upper (Read-only) 0x10D 0x1A8 Read-only 10.7 Device Control Registers DCRs may be used to control various on-chip system functions, such as the operation of on-chip buses, peripherals, and certain processor function behaviors.
Page 357: Appendix A. Instruction Summary
Appendix A.2 on page 362 lists all PPC405 mnemonics, including extended mnemonics, alphabetically. A short functional description is included for each mnemonic. Appendix A.3 on page 388, lists all PPC405 instructions, sorted by primary and secondary opcodes. Extended mnemonics are not included in the opcode list.
Page 358 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual BD (16:29) An immediate field specifying a 14-bit signed twos complement branch displacement. This field is concatenated on the right with 0b00 and sign-extended to 32 bits. BF (6:8) Specifies a field in the CR used as a target in a compare or mcrf instruction.
Page 359: Instruction Format Diagrams
The instruction formats (also called forms) illustrated in Figure A-1 through Figure A-9 are valid combinations of instruction fields. Table A-2 on page -388 indicates which form is utilized by each PPC405 opcode. Fields indicated by slashes (/, //, or ///) are reserved. The figures are adapted from the PowerPC User Instruction Set Architecture.
Page 360: I-Form
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual A.1.2.1 I-Form Figure A-1. I Instruction Format OPCD A.1.2.2 B-Form Figure A-2. B Instruction Format OPCD AA LK 30 31 A.1.2.3 SC-Form Figure A-3. SC Instruction Format OPCD 30 31 A.1.2.4 D-Form...
Page 361: X-Form
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual A.1.2.5 X-Form Figure A-5. X Instruction Format OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD OPCD...
Page 362: Xfx-Form
OPCD A.2 List of Implemented Instructions—Alphabetical Table A-1 summarizes the PPC405 instruction set, including required extended mnemonics. All mnemonics are listed alphabetically, without regard to whether the mnemonic is realized in hardware or software. When an instruction supports multiple hardware mnemonics (for example, b, ba, bl, bla are all forms of b), the instruction is alphabetized under the root form.
Page 363 These alternate codings set BO = 1 only if the requested prediction differs from the standard prediction.See Branch Prediction on page 52 for more information. Table A-1. PPC405 Instruction Syntax Summary Mnemonic Operands Function Other Registers Changed Page RT, RA, RB Add (RA) to (RB).
Page 364 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page target Branch unconditional relative. ← (target – CIA) 6:29 ← CIA + EXTS(LI Branch unconditional absolute.
Page 365 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page bdnzf cr_bit, target Decrement CTR. Branch if CTR ≠ 0 AND CR = 0. cr_bit...
Page 366 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page bdzflr cr_bit Decrement CTR. Branch if CTR = 0 AND CR = 0 to address in LR.
Page 367 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page bflr cr_bit Branch if CR = 0 to address in LR. cr_bit Extended mnemonic for bclr 4,cr_bit ←...
Page 368 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page blectr [cr_field] Branch if less than or equal to address in CTR. Use CR0 if cr_field is omitted.
Page 369 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page bnelr [cr_field] Branch if not equal to address in LR. Use CR0 if cr_field is omitted.
Page 370 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page [cr_field], target Branch if not summary overflow. Use CR0 if cr_field is omitted. Extended mnemonic for bc 4,4∗cr_field+3,target...
Page 371 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page bsoctr [cr_field] Branch if summary overflow to address in CTR. Use CR0 if cr_field is omitted.
Page 372 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page clrlwi RA, RS, n Clear left immediate. (n < 32) ← (RA) 0:n−1 Extended mnemonic for rlwinm RA,RS,0,n,31 clrlwi.
Page 373 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page crnor BT, BA, BB NOR bit (CR BA ) with (CR BB ). Place result in CR BT .
Page 374 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page extrwi RA, RS, n, b Extract and right justify immediate. (n > 0) ← (RA) 32−n:31 (RS) b:b+n−1...
Page 375 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page lhau RT, D(RA) Load halfword from EA = (RA|0) + EXTS(D) and sign extend, ←...
Page 376 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page lwzu RT, D(RA) Load word from EA = (RA|0) + EXTS(D) and place in RT, ←...
Page 377 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page ← maclhw RT, RA, RB prod (RA) x (RB) signed 0:31 ← 16:31 16:31 temp...
Page 378 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page mfccr0 Move from special purpose register (SPR) SPRN. Extended mnemonic for mfctr mfspr RT,SPRN mfdac1...
Page 379 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page mtcrf FXM, RS Move some or all of the contents of RS into CR as specified by FXM field, ←...
Page 380 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page ← mulhhwu RT, RA, RB (RT) (RA) x (RB) unsigned 0:31 0:15 0:15 mulhhwu. CR[CR0] ←...
Page 381 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page ← nmaclhw RT, RA, RB nprod –((RA) x (RB) ) signed 0:31 ← 16:31 16:31...
Page 382 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page rotlwi RA, RS, n Rotate left immediate. ← (RA) ROTL((RS), n) Extended mnemonic for rlwinm RA,RS,n,0,31 rotlwi.
Page 383 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page stbux RS, RA, RB Store byte (RS) 24:31 in memory at EA = (RA|0) + (RB).
Page 384 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page RT, RA, RB Subtract (RB) from (RA). ← ¬ (RT) (RB) + (RA) + 1.
Page 385 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page subic RT, RA, IM Subtract EXTS(IM) from (RA). Place result in RT. Place carry-out in XER[CA].
Page 386 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page tlbwehi RS, RA Write TLBHI of the selected TLB entry from RS. Write the TID field of the selected TLB entry from the PID register.
Page 387 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-1. PPC405 Instruction Syntax Summary (Continued) Mnemonic Operands Function Other Registers Changed Page tweqi RA, IM Trap if (RA) equal to EXTS(IM). Extended mnemonic for twi 4,RA,IM twgei Trap if (RA) greater than or equal to EXTS(IM).
Page 388: List Of Instructions-By Opcode
OPCD in Figure A-1 through Figure A-9, beginning on page -360) in bits 0:5. Some instructions also have a secondary opcode field (shown as field XO in Figure A-1 through Figure A-9). PPC405 instructions, sorted by primary and secondary opcode, are listed in Table A-2.
Page 389 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-2. PPC405 Instructions by Opcode (Continued) Primary Secondary Opcode Form Mnemonic Operands Page Opcode mulchwu RT, RA, RB mulchwu. 140 (652) macchwu RT, RA, RB macchwu. macchwuo machhwuo.
Page 390 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-2. PPC405 Instructions by Opcode (Continued) Primary Secondary Opcode Form Mnemonic Operands Page Opcode 430 (942) nmaclhw RT, RA, RB nmaclhw. nmaclhwo nmaclhwo. maclhws 492 (972) RT, RA, RB maclhws.
Page 391 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-2. PPC405 Instructions by Opcode (Continued) Primary Secondary Opcode Form Mnemonic Operands Page Opcode crorc BT, BA, BB cror BT, BA, BB bcctr BO, BI bcctrl rlwimi RA, RS, SH, MB, ME rlwimi.
Page 392 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-2. PPC405 Instructions by Opcode (Continued) Primary Secondary Opcode Form Mnemonic Operands Page Opcode mulhw RT, RA, RB mulhw. mfmsr dcbf RA, RB lbzx RT, RA, RB 104 (616) RT, RA neg.
Page 393 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-2. PPC405 Instructions by Opcode (Continued) Primary Secondary Opcode Form Mnemonic Operands Page Opcode mullw 235 (747) RT, RA, RB mullw. mullwo mullwo. dcbtst RA,RB stbux RS, RA, RB...
Page 394 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table A-2. PPC405 Instructions by Opcode (Continued) Primary Secondary Opcode Form Mnemonic Operands Page Opcode lwbrx RT, RA, RB RA, RS, RB srw. tlbsync lswi RT, RA, NB sync...
Page 395: Appendix B. Instructions By Category
Appendix B. Instructions by Category Instruction Set on page 157 contains detailed descriptions of the instructions, their operands, and notation. Table B-1 summarizes the instruction categories in the PPC405 instruction set. The instructions within each category are listed in subsequent tables.
Page 396 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-2. Implementation-specific Instructions (Continued) Other Registers Mnemonic Operands Function Page Changed ← macchwsu RT, RA, RB prod (RA) x (RB) unsigned 0:31 ← 16:31 0:15 temp prod + (RT) 0:32 ←...
Page 397 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-2. Implementation-specific Instructions (Continued) Other Registers Mnemonic Operands Function Page Changed ← maclhws RT, RA, RB prod (RA) x (RB) signed 0:31 ← 16:31 16:31 temp prod + (RT) 0:32 ∧...
Page 398: Instructions In The Powerpc Embedded Environment
To meet the functional requirements of processors for embedded systems and real-time applications, the PowerPC Embedded Environment defines instructions that are not part of the PowerPC Architecture. Table B-3 summarizes the PPC405 instructions in the PowerPC Embedded Environment. Table B-3. Instructions in the IBM PowerPC Embedded Environment...
Page 399 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-3. Instructions in the IBM PowerPC Embedded Environment (Continued) Other Registers Mnemonic Operands Function Page Changed dcbz RA, RB Zero the data cache block which contains the EA (RA|0) + (RB).
Page 400: Privileged Instructions
TLB-update instructions executed by this processor have been received and completed by all other processors. For the PPC405, tlbsync is a no-op. tlbwe RS, RA,WS If WS = 0: Write TLBHI portion of the selected TLB entry from RS.
Page 401 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-4. Privileged Instructions (Continued) Other Registers Mnemonic Operands Function Page Changed mfspr RT, SPRN Move from SPR to RT, ← (RT) (SPR(SPRN)). Privileged for all SPRs except LR, CTR, TBHU, TBLU, and XER.
Page 402: Assembler Extended Mnemonics
These mnemonics encode to the opcodes of other instructions; the only benefit of extended mnemonics is improved usability. Code using extended mnemonics can be easier to write and to understand. Table B-5 lists the extended mnemonics required for the PPC405. Note for every Branch Conditional mnemonic: Bit 4 of the BO field provides a hint about the most likely outcome of a conditional branch.
Page 403 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed bdnzf cr_bit, target Decrement CTR. Branch if CTR ≠ 0 AND CR = 0. cr_bit...
Page 404 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed bdzf cr_bit, target Decrement CTR. Branch if CTR = 0 AND CR = 0. cr_bit...
Page 405 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed beqlr [cr_field] Branch, if equal, to address in LR. Use CR0 if cr_field is omitted.
Page 406 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed [cr_field,] target Branch if greater than. Use CR0 if cr_field is omitted. Extended mnemonic for bc 12,4∗cr_field+1,target...
Page 407 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed [cr_field,] target Branch if less than. Use CR0 if cr_field is omitted. Extended mnemonic for bc 12,4∗cr_field+0,target...
Page 408 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed [cr_field,] target Branch, if not greater than. Use CR0 if cr_field is omitted. Extended mnemonic for bc 4,4∗cr_field+1,target...
Page 409 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed [cr_field,] target Branch if not summary overflow. Use CR0 if cr_field is omitted. Extended mnemonic for bc 4,4∗cr_field+3,target...
Page 410 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed [cr_field,] target Branch if summary overflow. Use CR0 if cr_field is omitted. Extended mnemonic for bc 12,4∗cr_field+3,target...
Page 411 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed [cr_field,] target Branch if unordered. Use CR0 if cr_field is omitted. Extended mnemonic for bc 12,4∗cr_field+3,target...
Page 412 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed cmpwi [BF,] RA, IM Compare Word Immediate. Use CR0 if BF is omitted. Extended mnemonic for...
Page 413 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed mfccr0 Move from special purpose register (SPR) SPRN. Extended mnemonic for mfctr mfspr RT,SPRN mfdac1 mfdac2 See Table 10-3 on page 354 for listing of valid SPRN values.
Page 414 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed mtccr0 Move to SPR SPRN. Extended mnemonic for mtctr mtspr SPRN,RS mtdac1 mtdac2 See Table 10-3 on page 354 for listing of valid SPRN values.
Page 415 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed rotlwi RA, RS, n Rotate left immediate. ← (RA) ROTL((RS), n) Extended mnemonic for rlwinm RA,RS,n,0,31 rotlwi.
Page 416 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-5. Extended Mnemonics for PPC405 (Continued) Other Registers Mnemonic Operands Function Page Changed subic RT, RA, IM Subtract EXTS(IM) from (RA). Place result in RT. Place carry-out in XER[CA].
Page 417: Storage Reference Instructions
12,RA,IM B.5 Storage Reference Instructions The PPC405 uses load and store instructions to transfer data between memory and the general purpose registers. Load and store instructions operate on byte, halfword and word data. The storage reference instructions also support loading or storing multiple registers, character strings, and byte-reversed data. Table B-6 shows the storage reference instructions available for use in the PPC405.
Page 418 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-6. Storage Reference Instructions Other Registers Mnemonic Operands Function Page Changed RT, D(RA) Load byte from EA = (RA|0) + EXTS(D) and pad left with zeroes, ← (RT) 0 || MS(EA,1).
Page 419 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-6. Storage Reference Instructions (Continued) Other Registers Mnemonic Operands Function Page Changed lswx RT, RA, RB Load consecutive bytes from EA=(RA|0)+(RB). Number of bytes = XER[TBC]. Stack bytes into words in CEIL(...
Page 420: Arithmetic And Logical Instructions
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-6. Storage Reference Instructions (Continued) Other Registers Mnemonic Operands Function Page Changed stswi RS, RA, NB Store consecutive bytes in memory starting at EA=(RA|0). Number of bytes = 32 if NB = 0, else = NB.
Page 421 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-7. Arithmetic and Logical Instructions (Continued) Other Registers Mnemonic Operands Function Page Changed addc RT, RA, RB Add (RA) to (RB). Place result in RT. addc. Place carry-out in XER[CA].
Page 422 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-7. Arithmetic and Logical Instructions (Continued) Other Registers Mnemonic Operands Function Page Changed divw RT, RA, RB Divide (RA) by (RB), signed. Place result in RT. divw. CR[CR0]...
Page 423 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Table B-7. Arithmetic and Logical Instructions (Continued) Other Registers Mnemonic Operands Function Page Changed ¬ RA, RS, RB OR (RS) with (RB). Place result in RA. orc. CR[CR0] RA, RS, IM OR (RS) with ( IM).
Page 424: Condition Register Logical Instructions
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual B.7 Condition Register Logical Instructions CR logical instructions combine the results of several comparisons without incurring the overhead of conditional branching. These instructions can significantly improve code performance if multiple conditions are tested before making a branch decision.
Page 425: Comparison Instructions
Comparison instructions perform arithmetic and logical comparisons between two operands and set one of the eight condition code register fields based on the outcome of the comparison. Table B-10 shows the comparison instructions supported by the PPC405. Table B-10. Comparison Instructions...
Page 426: Rotate And Shift Instructions
B.10 Rotate and Shift Instructions Rotate and shift instructions rotate and shift operands which are stored in the general purpose registers. Rotate instructions can also mask rotated operands. Table B-11 shows the PPC405 rotate and shift instructions. Table B-11. Rotate and Shift Instructions...
Page 427: Cache Control Instructions
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual B.11 Cache Control Instructions Cache control instructions allow the user to indirectly control the contents of the data and instruction caches. The user may fill, flush, invalidate and zero blocks (16-byte lines) in the data cache. The user may also invalidate congruence classes in both caches and invalidate individual lines in the instruction cache.
Page 428: B.13 Tlb Management Instructions
TLB-update instructions executed by this processor have been received and completed by all other processors. For the PPC405, tlbsync is a no-op. tlbwe RS, RA,WS If WS = 0: Write TLBHI portion of the selected TLB entry from RS.
Page 429: B.14 Processor Management Instructions
Revision 1.02 - September 10, 2007 Preliminary User’s Manual B.14 Processor Management Instructions The processor management instructions move data between GPRs and SPRs and DCRs in the PPC405; these instructions also provide traps, system calls and synchronization controls. Table B-15. Processor Management Instructions...
Page 430: Appendix C. Code Optimization And Instruction Timings
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Appendix C. Code Optimization and Instruction Timings The code optimization guidelines in “Code Optimization Guidelines” and the information describing instruction timings in Instruction Timings on page 431 can help compiler, system, and application programmers produce high- performance code and determine accurate execution times.
Page 431: C.1.4 Cr Dependencies
PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual Moving new code and data into the cache arrays occurs at the speed of external memory. Much faster execution is possible when all code and data is available in the cache. Organizing code to uniformly use minimizes the use of congruent addresses.
Page 432: C.2.2 Branches
(by examining sign bit extension) to reduce the number of cycles necessary to complete the multiplication. The PPC405 also supports multiply accumulate (MAC) instructions and multiply instructions having halfword operands. Word and halfword multiply instructions are pipelined in the execution unit and use the same multiplication hardware.
Page 433: C.2.4 Scalar Load Instructions
C.2.4 Scalar Load Instructions Generally, the PPC405 executes cacheable load instructions that hit in the data cache array or line fill buffer, or non cacheable load instructions that hit in the line fill buffer (when enabled), in one cycle. However, the pipelined nature of load instructions can even cause loads that hit in the cache or line fill buffer to appear to take extra cycles under some conditions.
Page 434: C.2.5 Scalar Store Instructions
In the following example, the string contains 21 bytes. The first three bytes do not begin on a word boundary, and the final two bytes do not end on a word boundary. The PPC405 handles any unaligned leading bytes as a special case, then moves as many bytes as aligned words as possible, and finally handles any unaligned trailing bytes as a special case.
Page 435: C.2.8 Loads And Store Misses
(See the Cache Operations on page 69 for more information.) Because the PPC405 can execute instructions that follow load misses if no load-use dependency exists, the load and the “using” instruction should be separated by “non-using” instructions whenever possible. The number of load miss penalty cycles incurred by a load that misses in the DCU or DCU line fill buffer is reduced by one cycle for every non-use instruction following the load.
Page 436 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual AMCC Proprietary...
Page 437: Index
AMCC Confidential and Proprietary...
Page 438 DAC debug events bnsa CCR0 bnsctr clrlslwi bnsctrl clrlslwi. bnsl clrlwi bnsla clrlwi. bnslr clrrwi bnslrl clrrwi. bnua cmpi AMCC Confidential and Proprietary...
Page 439 See also interrupts dcbt extended memonics functions beqlr dcbtst extended menmonics functions blectrl dcbz bnlctrl functions extended mnemonicd dccci bngla functions extended mnemonics DCCR alphabetical bctr dcread bctrl functions bdnz AMCC Confidential and Proprietary...
Page 440 AMCC Confidential and Proprietary...
Page 441 AMCC Confidential and Proprietary...
Page 442 FIT (fixed interval timer) andc. interrupts, causes andi. interrupts, register settings andis. fixed interval timer. See FIT bcctr bcctrl GPR0-GPR31 bcla bclr H, I, J, K bclrl IAC1–IAC4 icbi function cmpi icbt cmpl function cmpli iccci cntlzw function AMCC Confidential and Proprietary...
Page 443 AMCC Confidential and Proprietary...
Page 444 TLB miss wrtee interrupts wrteei alignment register settings xori data storage instruction fields register settings instruction formats defined diagrams DTLB miss AMCC Confidential and Proprietary...
Page 445 AMCC Confidential and Proprietary...
Page 446 CCR0 secondary opcodes DAC1–DAC2 DBCRx SLER DBSR DCCR slw. DCWR slwi DEAR slwi. device control speculative access during debug exceptions DVC1–DVC2 SPRG0-SPRG7 SPRs (special purpose registers) AMCC Confidential and Proprietary...
Page 447 AMCC Confidential and Proprietary...
Page 448 U, V, W user mode registers USPRG0 virtual memory access protection pages watchdog timer WDT (watchdog timer) interrupts, causes interrupts, register settings wrtee wrteei xori AMCC Confidential and Proprietary...
Page 449: Revision Log
Jan. 24, 2007 Initial creation of separate 405 processor UM. 1.01 Feb. 19, 2007 Add bit definitions to CCR0 register for 405EZ chip. Change clock source for 405EZ to CPU. 1.02 Sept. 10, 2007 Correct AMCC phone numbers. AMCC Proprietary...
Page 450 PPC405 Processor Revision 1.02 - September 10, 2007 Preliminary User’s Manual AMCC Proprietary...

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1 Overview

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