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6. Appendix
Table 6.6.
Function of Each Register < 2 / 4 >
I/O address
03FAH
IIR : Interrupt Identification Register
D7
0
bit2
bit1
bit0
0
0
1
1
1
0
0
1
0
0
03FBH
LCR : Line Contror Regester
D7
68
Description
D6
D5
D4
D3
D2
0
0
0
0
Interrupt details
Priority
Interrupts are not generated.
1
Generated by overrun, parity, framing error or break
0
1 (high)
interrupt.
Cleared when the line status register is read.
Generated when the receive buffer register is ready.
0
2
Cleared when the receiving buffer is read.
Generated when the transmitter holding register is
0
3
empty. Cleared when the IIR is read or when
transmitted data is written to THR.
Modem status interrupt is generated.
0
4 (low)
(CTS, DSR, RI, CD)
Cleared when the modem status register is read.
D6
D5
D4
D3
D2
0 : Disable parity
1 : Enable parity
0 : Odd parity
1 : Even parity
0 : Disable stick parity
1 : Enable stick parity
0 : Break signal off
1 : Send break signal
DLAB (Divisor Latch Access Bit)
In order to access the divisor latch register, you need to set the bit
to 1. To access another register, set the bit to 0.
D1
D0
1: Do not generate interrupts
0: Generate interrupts
Description
D1
0
D1
D0
0
1
1
0 : 1 STOP bit
1 : 1.5 STOP bits at 5-bit length
2 STOP bits at 6-, 7-, or 8-bit length
D0
Bit table
0
5
1
6
0
7
1
8
BX-955Sx Series User's manual
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