Yamaha YSP-1 Service Manual page 52

Digital sound projector
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A
B
C
YSP-1
SCHEMATIC DIAGRAM (DSP 2/2)
1
Page 53
G7
to INPUT (2)_CB9
ANALOG IN
2
SUBWOOFER OUT
3
DIGITAL IN
0.4
3.3
0
0
0
4.3
3.3
4
0
0
DIR
3.3
3.3
4.1
1.5
1.6
A-1
1.6
3.3
3.3
0
0
5
6
0
0
1.3
1.3
3.3
0.5
0
3.3
3.3
3.3
7
1.3
1.3
0
0
3.3
0
3.2
3.3
1.3
1.3
0
0
0
3.3
3.3
8
3.3
9
POINT A-1 pin 28 of IC300
POINT C-1 pin 13 of IC304
10
★ All voltages are measured with a 10MΩ/V DC electronic volt meter.
★ Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
52
D
E
F
3.3
3.2
3.2
3.2
3.4
3.2
3.4
3.3
0
0.1
0.1
C-1
3.2
0
CPU
3.3
3.3
3.3
3.4
3.3
1.6
0
0
3.3
0
2.3
0.1
3.4
Key Input (A-D) Pull-Up Resistance 10 k-ohms
3.2
3.3
Ohm
0 k
+1.2 k
3.2
3.3
V
~ 0.30
~ 0.70
3.2
ADKEY 0
VOLUME
3.3
3.3
94pin A/D2
+
INPUT
3.3
3.2
ADKEY 0
VOLUME
0
95pin A/D1
-
0
3.2
3.1
3.2
0
0
0
0
0
0
3.3
0
1.3
1.3
0
1.3
1.3
0
0
3.3
3.0
0
1.3
1.3
0
0
MAIN DECODER
3.3
0
~
0
0
~
1.2
1.6
IC312: NJM2068MD
IC311: AK5381VT-E2
96kHz 24Bit ∆Σ A/D Converter
Dual OP-Amp.
VA
6
OUT
1
8
+V
1
CC
–IN
1
2
7
OUT
2
+
+
+IN
3
6
–IN
AINL
1
2
2
Modulator
–V
4
5
+IN
CC
2
AINR
1
Modulator
Voltage
VCOM
4
Reference
15
3
16
CKS2
CKS1
CKS0
G
H
Page 53
I7
Page 53
F7
to INPUT (2)_W10
to INPUT (3)_W11
3.4
3.2
0.1
2.5
0
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.3
3.2
3.2
3.2
0.5
3.2
3.2
3.3
3.3
1.6
3.2
1.7
1.6
1.6
~
POST
0
0
PROSESSER
0
0
~
~
0.6
~
~
1.2
0
2.5
0
IC310: AK4381VT
192kHz 24Bit 2ch DAC
AGND
VD
DGND
MCLK
MCLK
5
7
8
11
1
14
Clock
De-emphasis
Clock
13
Control
Divider
Divider
CSN
6
µP
Decimation
16
LRCK
CCLK
7
10
Interface
Filter
CDTI
8
15
12
Decimation
12
SCLK
8X
SCF
Filter
LRCK
Interpolator
Modulator
4
Audio
11
BICK
2
Data
Serial I/O
SDTI
9
SDTO
3
Interface
8X
10
Interface
SCF
Interpolator
Modulator
9
13
14
5
PDN
DIF
PDN
I
J
K
14.2
8
2
4.3
1
DAC
3
7.0
4
4.3 0
1.6
5.0
0.1
1.7
1.6
1.6
0
3.2
3.2
5
2.6
3.2
0
7
6
13.7
2.6
3.2
13.7
A/D
~
1.6
5.0
1.6
5.0
2.5
2.5
1.7
0
3.2
2.5
5.0
0
2.5
5.0
2.5
2.5
0
2.5
0
0
IC307-309: AK4121VF
Asynchronous Sample Rate Converter
PDN
DEM0 DEM1
SMUTE
TVDD
VDD DNSS
(MCLK)
PDN
SDTO
Serial
Serial
ILRCK
Audio
Sample
VDD
Audio
OLRCK
I/F
De-em
soft
Rate
I/F
filter
VSS
Converter
mute
IBICK
OBICK
DZFL
DZFR
CMODE2
AVSS
AOUTL+
CMODE1
PLL
AOUTL-
FILT
CMODE0
AOUTR+
AOUTR-
IDIF2
IDIF1
IDIF0
ODIF1
ODIF0
FILT
1
24
VDD
AVSS
2
23
DVSS
PDN
3
22
TVDD
SMUTE
4
21
MCLK
DEM0
5
20
OLRCK
MEM1
6
19
OBICK
ILRCK
7
18
SDTO
IBICK
8
17
ODIF1
SDTI
9
16
ODIF0
IDIF0
10
15
CMODE2
IDIF1
11
14
CMODE1
IDIF2
12
13
CMODE0
L
M
N
IC300: LC89057W-VF4-E
192kHz 24Bit 8ch DAC
DZF
Audio
10
MCLK
I/F
LOUT1+
LRCK
2
17
SCF
DAC
DATT
LOUT1–
1
9
BICK
ROUT1+
48
14
SDTI1
SCF
DAC
DATT
ROUT1–
15
SDTI2
47
16
SDTI3
LOUT2+
46
SCF
DAC
DATT
PCM
13
SDTI4
LOUT2–
45
Control
ROUT2+
44
SCF
DAC
DATT
3-wire
Register
ROUT2–
or 12C
43
LOUT3+
42
22
DCLK
SCF
DAC
DATT
LOUT3–
41
25
DSDL1
26
DSDR1
ROUT3+
40
SCF
DAC
DATT
27
DSDL2
ROUT3–
39
28
DSDR2
LOUT4+
38
DSD
SCF
DAC
DATT
DSDL3
29
LOUT4–
37
30
DSDR3
ROUT4+
33
SCF
DAC
DATT
23
DSDL4
ROUT4–
32
24
DSDR4
IC301: SN74LV245APWR
Octal Bus Transceiver with 3-state Outputs
0.1
DIR
1
20
Vcc
0
2
19
A1
OE
A2
3
18
B1
4
17
A3
B2
A4
5
16
B3
6
15
A5
B4
A6
7
14
B5
8
13
A7
B6
A8
9
12
B7
10
11
GND
B8
IC302: YSS948-VZ
Post Processor
ClkGen
MicomIF
XI
PLL
nMUTE
XO
ZEROFLG
Firmware download circuit
Regiser
Internal operation clock
nINT
nIC
STATUS7-0
Result of Status change detection
TEST
Bypass
to each control section
SDI
SDO
Decoder
SDI3-0
SDO3-0
DSP
memory
SDIMCK
SDOMCK
SDIBCK
SDOBCK
SDIWCK
SDOWCK
Dividing/Switcing
EMS
IC303: S-29630AFJA
CMOS SERIAL EEPROM
VCC
Memory array
Address
decoder
GND
Data register
Output buffer
DO
DI
Mode decode logic
CS
CS
1
8
VCC
SK
2
7
NC
SK
Clock generator
DI
3
6
TEST
DO
4
5
GND
IC305: YSS930-SZ
DSP
MICROPROCESSOR
INTERFACE
PROGRAM
COEFFICIENT
ADDRESS
RAM
RAM
RAM
CONTROL REGISTER
50 bit
1024
16 bit
1024
17 bit
256
CONTROL
SIGNALS
SDBCK
SDWCK
SDI0
SDO0
SDI1
SDO1
SDI2
SDO2
SDI3
SDO3
32 bit DSP Core
SDI4
SDO4
SDI5
SDO5
SDI6
SDO6
SDI7
SDO7
DSP INTERNAL
OPERATING CLOCK
CK (30.72~40.96MHz)
EXTERNAL RAM
INTERFACE
PLL

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