Toshiba 20VL44 Service Manual page 50

1.2 gm5221 Family Features
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Intelligent Image Processing™
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Fully programmable zoom ratios
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High-quality shrink capability from UXGA resolution
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Programmable coefficients for variable sharpness control
• RealRecovery™ provides full color recovery image for
refresh rates higher than those supported by the LCD panel
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Analog RGB Input Port
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Supports SDTV RGB inputs in interlaced mode
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Supports EDTV (480p) up to 1080i HDTV inputs
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Supports mid level clamp for YPbPr inputs
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Macro vision decoding
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Supports up to 162 MHz (SXGA 75Hz / UXGA 60Hz)
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On-chip high-performance PLLs (single reference crystal
required)
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Composite-sync, Sync-on-Green (SOG) and Sync-on-Y
(SoY) support
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Input format detection
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Phase and image positioning
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Ultra-Reliable DVI-Compliant Input Port
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Operating up to 165 MHz (up to UXGA 60Hz)
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Direct connect to all DVI 1.0-compliant transmitters
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High-bandwidth Digital Content Protection (HDCP)
Note: HDCP function is available H version only.
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CCIR-656 8-bit Video Input Port
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Supporting NTSC / PAL interlaced and progressive
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Direct connect to commercially available video decoders
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Spatial de-interlacing
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Advanced Color Management
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Programmable gamma correction (CLUT)
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TV color controls including hue and saturation controls
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Full color matrix allows end-users to experience the same
colors as viewed on CRTs and other displays (e.g. sRGB
compliance)
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Advanced Active Color Management ™ (ACM-II) provide
flesh-tone compensation and image enhancement for video
preset modes like sport, nature .
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Adaptive Contrast and Color™ (ACC) ensures full dynamic
range is used in video content
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On-chip Versatile OSD Controller
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On-chip RAM for high-quality programmable menus
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1, 2 and 4-bit per pixel character cells
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Horizontal and vertical stretch of OSD menus
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Blinking, transparency and blending
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Supports two independent OSD menu rectangles
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Proportional fonts
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Embedded X86 On-chip Microcontroller
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High-performance X86 MCU with on-chip RAM and ROM
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External parallel ROM or serial SPI ROM interface
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Unified memory architecture simplifies chip programming
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23 general-purpose inputs/outputs (GPIOs) available
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2-wire serial bus master to control NVRAM, video decoder
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Two DDC2Bi ports with DMA buffer to internal RAM
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Four PWM outputs for analog backlight control, audio, etc.
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General-purpose ADC's for keypad and temperature sensing
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Integrated reset circuit
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Slow clock mode for 50mW sleep mode power consumption
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JTAG debug / ICE support for firmware debugging
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Built-in Test Pattern Generator
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Simplifies manufacturing / test
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Energy Spectrum Management (ESM™)
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Digital clock spectrum management
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Eliminates EMI suppression components and shielding
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Built-in LVDS Transmitters
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Four channel 6/8-bit LVDS transmitter
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Support for 8 or 6-bit panels with high-quality dithering
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Single / double wide up to SXGA 75Hz output
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Pin swap, odd / even swap and red / blue group swap of RGB
outputs for flexibility in board layout
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Highly integrated System-on-a-Chip
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All system clocks synthesized from a single external crystal
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50mW power saving mode
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5-Volt tolerant inputs
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Two Layer PCB support
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On-chip reset feature to eliminate external reset component
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Integrated Schmitt trigger for HSYNC and VSYNC
PACKAGE
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208-pin PQFP
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3.3V IO and 1.8V core power supplies