Aiwa XP-V311 Service Manual page 17

IC, µPD789405AGC-013
Pin No. Pin Name I/O
1 VDO1 — Positive polarity power supply (except for port section).
2 BIAS — Feeding the LCD drive power supply voltage.
3-5 VLC0-VLC2 — LCD drive power supply voltage.
6 VSS1 — Ground potential (except for port section).
7-10 COM0-COM3 O Common signal output from LCD controller/driver.
11-38 S0-S27 O Segment signal output from LCD controller/driver.
39 AVDD — A/D comparator analog power supply.
40 AVREF — A/D comparator reference voltage.
41-47 ANI6-0 I Analog input signal to A/D comparator.
48 AVSS — A/D comparator ground potential.
External interrupt input whose effective edge (rise-up or fall-down or both edges of
49-52 INTP3-INTP0 I
rise-up and fall-down) can be specified.
53 TO2 O Output signal from 8-bit timer (TM02).
54 SI I Serial data input signal of serial interface.
55 SO O Serial data output signal of serial interface
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56 SCK I/O Serial clock input/output signal of serial interface
Port 5.
4-bit N-channel open-drain input/output port.
57-60 P53-P50 I/O Input or output; can be specified in units of 1 bit.
When it is used as an input port, built-in pull-up resistor can be used as specified by
mask option.
Port0.
4-bit input/output port.
61-64 P03-P00 I/O Input or output; can be specified in units of 1 bit.
When it is used as an input port, built-in pull-up resistor can be used as specified by
software
Port 4.
8-bit input/output port.
65, 66 P47, P46 I/O Input or output; can be specified in units of 1 bit.
When it is used as an input port, built-in pull-up resistor can be used as specified by
software.
_____________
67 RESET I System reset input.
68 X2 —
Terminal to connect external crystal for main system clock oscillation.
69 X1 I
70 VSS0 — Ground potential of port section.
71 VDD0 — Positive polarity power supply for port section.
72 XT2 —
Terminal to connect external crystal for sub system clock oscillation.
73 XT1 I
74 IC/VPP — This pin is internally connected. Connect this pin directly to Vss
75-80 P45-P40 I Key-return signal detection input signal.
Description
or Vss .
0 1
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IC, LA9253M
Pin No. Pin Name I/O
1 FIN1 I
2 FIN2 I
Pick-up signal input.
3 TIN1 I
4 TIN2 I
5 REF1 I Pin designed for reference voltage.
6 VREF O Reference voltage output.
7 LDS I APC monitor voltage input.
8 LDD O APC output.
9 GND — GND.
10 LDOF I laser OFF pin (H: ON L: OFF).
11 ODRV I Speed switch pin (H: double L: normal speed).
12 AGON I AGC ON pin (H: ON L: OFF).
13 EFBL I FE balance adjustment pin.
14 TESO O TE signal output for TES.
15 TESI I TE input for TES formation.
16 TES O TES output.
17 HFL O HFL signal output.
18 TE O TE signal output.
19 TE- I Minus input for TE gain design.
20 FE O FE signal output.
21 FE- I Minus input for FE gain design.
22 RFEV O RF envelop signal output.
23 N/C — Pin N/C.
24 BH I Capasitance connection pin for RF bottom clamp.
25 PH I Capasitance connection pin for RF gain design.
26 N/C — Pin N/C.
27 RF O RF signal output.
28 RF- I Minus input for RF signal gain design.
29 RFSW I Switch for equalizer design when RF has double speed.
30 VCC — Power supply.
Description
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