Control Register; Sampling Rate And Debounce Length - IBM EM78M611E Specification

EM78M611E
Universal Serial Bus Series Microcontroller
Pattern Detect Application (PDA) can calculate the length of one pattern and interrupt
the MCU while the serial signal is transiting from high to low (or vise-versa). Then the
MCU reads the length value from a specified register.

8.9.2 Control Register

The PDA includes an enable control bit, one control register and 4-length counter
registers in 0x10 ~0x13.
IOCA [2] PDA Enable Control Bit
When this bit is set, the PDA function starts and the P92 and P93 become input pin
automatically to sample the serial signal.
RB (PDA Control Register) Default Value: (0B_0000_0000)
Bit 7
SE2.F
This register is used to define two parameters of PDA function; signal sampling rate
and debounce length. When a pattern ends, the value in the counter is loaded into its
respective register and the RB[6] or RB[7] is set to indicate which type of pattern (high
or low) is at its end or which type of pattern counter is on overflow.
R10 (P.92 Low Pattern Counter)
This register records the length of P.92 in low status.
R11 (P.92 High Pattern Counter)
This register records the length of P.92 in high status.
R12 (P.93 Low Pattern Counter)
This register record the length of P.93 in low status.
R13 (P.93 High Pattern Counter)
This register records the length of P.93 in high status.
R10~R13 function as general registers if this function is not enabled. Once the enabled
bit is set, these four registers will be loaded with the value of the pattern counter.

8.9.3 Sampling Rate and Debounce Length

Although the two-pattern detect pins are separate, and each pin has its own pattern
counter, both pins use the same Sampling Rate and Debounce Length parameters.
The PDA samples the serial signal every fixed interval. The pattern counter will be
incremented by one at sampling time if the signal remains unchanged. If the signal is at
26 • • • •
0 : disable PDA function
1 : enable PDA function
Bit 6 Bit 5
SE1.F SR.2
0: low pattern
1: high pattern
Bit 4 Bit 3 Bit 2
SR.1 SR.0
Product Specification (V1.1) 11.22.2006
(This specification is subject to change without further notice)
Bit 1 Bit 0
DB2 DB1 DB0