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Related Manuals for Tews Technologies TVME8240
Summary of Contents for Tews Technologies TVME8240
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Page 1: User Manual
TVME8240 Single Board Computer ® with IndustryPack Interface Version 1.2 User Manual Issue 1.2.9 December 2009 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com... - Page 2 MPC8240 250 MHz, 64 MB SDRAM, document at any time without notice. 1 + 8 MB FLASH, Fast Ethernet, Front Panel I/O TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein. Style Conventions Hexadecimal characters are specified with prefix 0x, i.e.
- Page 3 Added Weight to Technical Information Section Response to VME System Reset has changed September 2005 Added VME Bus Error Interrupt capability August 2006 1.2.9 New Notation for User Manual and Engineering Documentation December 2009 TVME8240 User Manual Issue 1.2.9 Page 3 of 70...
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Page 4: Table Of Contents
EPIC Register Settings....................27 4.2.2.1 Global Configuration Register (GCR) ............27 4.2.2.2 EPIC Interrupt Configuration Register (EICR) ..........27 4.2.2.3 Serial Interrupt Vector / Priority Registers (SVPR) ........27 4.2.2.4 EPIC Register Programming.................27 I2C..............................28 4.3.1 I2C EEPROM........................28 TVME8240 User Manual Issue 1.2.9 Page 4 of 70... - Page 5 9.2.2 VME System Controller Jumper ...................56 LEDs ............................57 9.3.1 FAIL LED ........................57 9.3.2 FUSE LED ........................57 9.3.3 ACT LED........................57 9.3.4 SYS LED........................57 Switches............................58 9.4.1 RST Switch ........................58 9.4.2 ABT Switch ........................58 TVME8240 User Manual Issue 1.2.9 Page 5 of 70...
- Page 6 11.8 Power Requirements .........................68 11.9 IndustryPack Interface ......................69 11.9.1 Logic Interface ......................69 11.9.2 I/O Interface ........................69 11.10 Physical Data..........................70 11.10.1 MTBF ..........................70 11.10.2 Temperature .........................70 11.10.3 Weight...........................70 11.10.4 Humidity........................70 11.10.5 Form Factor ........................70 TVME8240 User Manual Issue 1.2.9 Page 6 of 70...
- Page 7 List of Figures FIGURE 1-1 : BLOCK DIAGRAM TVME8240 FRONT I/O ................10 FIGURE 1-2 : BLOCK DIAGRAM TVM8240 BOARD LAYOUT FRONT I/O ...........10 FIGURE 10-1 : BOARD I/O OVERVIEW......................55 List of Tables TABLE 1-1 : FEATURES TVME8240.........................9 TABLE 2-1 : PCI ARBITER ASSIGNMENT .....................13 TABLE 2-2 : PCI IDSEL ASSIGNMENT......................13...
- Page 8 TABLE 10-11 : SERIAL PORT B DB9 MALE CONNECTOR (RS232)............64 TABLE 10-12 : SERIAL PORT B DB9 MALE CONNECTOR (RS422)............65 TABLE 10-13 : LAN CONNECTOR 8P RJ45....................65 TABLE 12-1 : MTBF DATA..........................70 TVME8240 User Manual Issue 1.2.9 Page 8 of 70...
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Page 9: Introduction
1 Introduction The TVME8240 is a VME single slot Single Board Computer (SBC) using the Motorola MPC8240 Embedded PowerPC Processor. The board provides four single IndustryPack (IP) slots supporting single and double-sized IP modules running at 8 MHz or 32 MHz and front I/O ribbon cable connectors. -
Page 10: Block Diagram
10BaseT/ 50 pin 50 pin 50 pin 50 pin 100BaseT 4 x 50 pin Flat Cable Connector Figure 1-1 : Block Diagram TVME8240 Front I/O TVME8240 IP Slot A IP Slot B Status IP Slot C IP Slot D PCI Expansion Figure 1-2 : Block Diagram TVM8240 Board Layout Front I/O TVME8240 User Manual Issue 1.2.9... -
Page 11: Description
• Bank 1 consists of four 1 M x 16 bit on board FLASH devices providing a total of 8 Mbyte 64 bit wide Memory FLASH. 2.2.2 SDRAM Memory The TVME8240 provides four 8 M x 16 bit SDRAM devices, building up 64 Mbyte 64 bit wide SDRAM memory. 2.2.3 NVRAM / Real-Time Clock The TVME8240 uses an ST M48T59 compatible device to provide 8 KB of non-volatile static RAM and real-time clock. -
Page 12: 16550 Compatible Dual Uart
2.2.4 16550 compatible Dual UART The TVME8240 uses the Exar XR16C2550 16550 compatible Dual UART with a 1.8432 MHz clock- oscillator providing two asynchronous serial ports. Please refer to the XR16C2550 manual for details. 2.2.5 Utility Registers The TVME8240 provides some additional registers for board control and status functions. -
Page 13: Pci Arbiter Assignment
Table 2-1 : PCI Arbiter Assignment 2.3.2 PCI IDSEL Assignment The MPC8240 CPU provides capability for generating PCI configuration cycles. The TVME8240 uses the following IDSEL assignment for the various on board PCI devices. Device Number Address Line PCI Device... -
Page 14: Vme Bus Interface
2.4 VME Bus Interface The TVME8240 uses the Universe-II VME PCI Bridge (Tundra) to build the VME interface. The Universe-II VME PCI Bridge provides a 32 bit address / 32 bit data VME interface. Please refer to the Universe-II manuals for details. -
Page 15: Asynchronous Serial Interface
2.8 Asynchronous Serial Interface The TVME8240 provides two asynchronous serial interface ports used by the on board Dual UART. Port A is a fix RS232 port. Port B can be configured for RS232 or RS422 by an adapter card. Both serial ports are available on DB9 male connectors on the front panel or on the VME P2 connector. -
Page 16: Status Indicators
Table 2-4 : Status Indicators All status indicators are ON during a board reset. 2.11 Reset Switch The TVME8240 provides a momentary RESET switch accessible on the front panel. The RESET switch can be used to generate a board hardware reset. 2.12 Abort Switch The TVME8240 provides a momentary ABORT switch accessible on the front panel. -
Page 17: Address Maps
3 Address Maps The TVME8240 uses the MPC8240 address map B in host mode. The following address maps reflect MPC8240 configuration register settings done by board initialization software. 3.1 Address Map - Processor View Processor Address Size Description (Byte) Start... -
Page 18: Address Map - Pci Memory Master View
Boot FLASH (8 bit wide) Table 3-4 : Address Map – PCI Memory Master View On the TVME8240 the MPC8240 responds as a target to PCI Memory cycles for accessing SDRAM, PCI accessible MPC8240 EUMB, Memory FLASH, Peripheral Devices and Boot FLASH. -
Page 19: Address Map - Pci I/O Master View
For read or write accesses to the Peripheral Devices only 8 bit (byte) transfer sizes are allowed. For the NVRAM / RTC register map please refer to the M48T59 device documentation. For the UART register map please refer to the XR16C2550 documentation. TVME8240 User Manual Issue 1.2.9 Page 19 of 70... -
Page 20: Address Map - Utility Register Detail
A board reset will perform a general board hardware reset, re-configuration of the IP FPGA, PCI reset and CPU reset. If the TVME8240 is the VME bus system controller, a board reset will also trigger a VME bus system reset. -
Page 21: Status Register (0Xffe4_0001)
Write as '0' Reserved Undefined for Reads Write as '0' Reserved Undefined for Reads Write as '0' Reserved Undefined for Reads Write as '0' Reserved Undefined for Reads. Reserved Write as '0' TVME8240 User Manual Issue 1.2.9 Page 21 of 70... -
Page 22: Table 3-10: Led Register
Undefined for Reads Write as '0' Reserved Undefined for Reads. Write as '0'. Reserved (LSB) Undefined for Reads Table 3-10: LED Register TVME8240 User Manual Issue 1.2.9 Page 22 of 70... -
Page 23: Mpc8240
Configuration Register settings are shown in little endian order. Since on the TVME8240 the MPC8240 processor and peripheral logic operates in big endian mode, software must either use byte reversed load / store instructions or byte-swap the values for the CONFIG_ADDR and CONFIG_DATA port access. -
Page 24: Configuration Register Settings
Clock Driver Control 0x0000 Register 0x78 Embedded Utilities Memory 0xFCF0_0000 Block Base Address (EUMBBAR) 0x80, Memory Starting Address 0x4040_4000, Registers 0x84 0x4040_4040 0x88, 0x8C Extended Memory Starting 0x0000_0000, Address Registers 0x0000_0000 TVME8240 User Manual Issue 1.2.9 Page 24 of 70... -
Page 25: Table 4-1 : Mpc8240 Configuration Register Settings
0xF4 Memory Control 0x0A40_0F8C Configuration Register 2 (MCCR2) 0xF8 Memory Control 0x0620_0000 Configuration Register 3 (MCCR3) 0xFC Memory Control 0x2500_2220 Configuration Register 4 (MCCR4) Table 4-1 : MPC8240 Configuration Register Settings TVME8240 User Manual Issue 1.2.9 Page 25 of 70... - Page 26 The MEMGO bit in the MCCR1 register (offset 0xF0) must not be set until all other memory configuration parameters have been appropriately configured. The DLL_RESET bit in the AMBOR register (offset 0xE0) must be explicitly set and then cleared by software during initialization. TVME8240 User Manual Issue 1.2.9 Page 26 of 70...
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Page 27: Mpc8240 Epic Register
4.2 MPC8240 EPIC Register The TVME8240 uses the MPC8240 EPIC in serial mode as the board interrupt controller. 4.2.1 EPIC Register Access The EPIC Registers are part of the MPC8240 Embedded Utility Memory Block (EUMB). The EUMB base address is set in the EUMBBAR Register. -
Page 28: I2C Eeprom
4.3 I2C The TVME8240 provides an on board I2C EEPROM for board specific data. 4.3.1 I2C EEPROM EEPROM Description Content Offset 0x00 Check sum see note below 0x01 Number Of Valid Bytes Following e.g. 0x06 0x02 Board Type (High Byte) -
Page 29: Flash Programming
5 FLASH Programming 5.1 8 bit Wide Socket Boot FLASH The TVME8240 provides 1 MB of 8 bit wide socket Boot FLASH using two 512 K x 8 bit 32-pin PLCC FLASH devices. The Boot FLASH address range is 0xFFF0_0000 to 0xFFFF_FFFF. -
Page 30: Table 5-2 : Boot Flash Auto Select Codes
SA12 64 K 0xFFFC_0000 - 0xFFFC_FFFF SA13 64 K 0xFFFD_0000 - 0xFFFD_FFFF SA14 64 K 0xFFFE_0000 - 0xFFFE_FFFF SA15 64 K 0xFFFF_0000 - 0xFFFF_FFFF Table 5-3 : Boot FLASH Sector Map TVME8240 User Manual Issue 1.2.9 Page 30 of 70... -
Page 31: Bit Wide On Board Memory Flash
5.2 64 bit Wide On Board Memory FLASH The TVME8240 provides 8 Mbyte of 64 bit wide board mounted Memory FLASH using four 1 M x16 bit FLASH devices. The Memory FLASH address range is 0xFF00_0000 to 0xFF7F_FFFF. The Memory FLASH data bus port width is 64 bit. -
Page 32: Table 5-4 : Memory Flash Command Cycles
6th Cycle Sequence Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read Reset Auto Select Write Chip Erase Sector Erase Table 5-4 : Memory FLASH Command Cycles TVME8240 User Manual Issue 1.2.9 Page 32 of 70... -
Page 33: Table 5-5 : Memory Flash Auto Select Codes
16 K 0xFF00_8000 - 0xFF00_BFFF 16 K 0xFF00_C000 - 0xFF00_FFFF 16 K 0xFF01_0000 - 0xFF01_3FFF … … … SA511 16 K 0xFF7F_C000 - 0xFF7F_FFFF Table 5-6 : Memory FLASH Sector Map TVME8240 User Manual Issue 1.2.9 Page 33 of 70... -
Page 34: Vme Bus Interface
6 VME Bus Interface The Tundra Universe-II VME PCI bridge is used as the TVME8240 VME PCI bridge. The Universe-II is accessible on both the VME bus and the TVME8240 PCI bus. Please refer to the Universe-II manual for a detailed description of the Universe-II VME PCI bridge. -
Page 35: Universe-Ii Reset Signals
II LINT# interrupt pins. To overcome this limitation the TVME8240 logic directly monitors the Universe- II VX_BERR output that is used for asserting VME bus errors. The TVME8240 VME bus error interrupt is handled via the Utility Registers in the Peripheral Devices address space. Please see the Address Map section for details. -
Page 36: Lan Interface
7 LAN Interface The Intel 21143 Ethernet controller is used for the TVME8240 Ethernet interface. The 21143 is accessible on the TVME8240 PCI bus. The 21143 INT# interrupt output is mapped to the serial interrupt no. 2 of the MPC8240 EPIC. -
Page 37: 21143 Configuration Eeprom
IEEE Network Address (6 Byte) 0x18 0x_yz_wx Controller_0 Dev# 0x1A 0x00 Controller_0 Info Leaf Offset 0x1B 0x0020 Reserved 0x1D 0x00 Reserved 0x1E 0x0000 Selected Connection Type 0x20 0x0800 Block Count 0x22 0x02 TVME8240 User Manual Issue 1.2.9 Page 37 of 70... -
Page 38: Table 7-2 : 21143 Configuration Eeprom Settings
0x01E0 FDX Bit Map 0x39 0x5000 TTM Bit Map 0x3B 0x1800 PHY Ins. Ind. 0x3D 0x00 Reserved 0x3E - 0x7B 0x00 Manufacturer_Reserved 0x0000 SROM_CRC Table 7-2 : 21143 Configuration EEPROM Settings TVME8240 User Manual Issue 1.2.9 Page 38 of 70... -
Page 39: 21143 Ports
Interrupts for GEP[1:0] inputs must be disabled. 7.5 Media Capabilities 10/100Base-TX Ethernet interface on the RJ45 front panel connector. AUI port for a 10Base-T or 10Base2 Ethernet interface on the VME P2 Connector. TVME8240 User Manual Issue 1.2.9 Page 39 of 70... -
Page 40: Ip Bus Interface
A FPGA is used on the PCI9030 local bus to build the IP interface and provide IP Interface Control Registers. 8.1 PCI9030 PCI Target Chip The PCI9030 provides four local spaces 0:3 that are used for the TVME8240 IP interface. Basic PCI9030 register configuration is loaded from a serial EEPROM after power-up or board reset. -
Page 41: Pci9030 Pci Header
HS CSR HS NxtCap HS CapID 0x0000_4C06 0x4C VPD Address VPD NxtCap VPD CapID 0x0000_0003 0x50 VPD Data 0x0000_0000 Read back Value after writing all 1's. Table 8-1 : PCI9030 PCI Header TVME8240 User Manual Issue 1.2.9 Page 41 of 70... -
Page 42: Local Configuration Register
Serial EEPROM / Interrupt Control & Status PROT_AREA / 0x0030_0049 INTCSR 0x50 Miscellaneous CNTRL 0x007A_4000 0x54 General Purpose I/O GPIOC 0x0224_9252 Table 8-2 : PCI9030 Local Configuration Register Shown values are register values after serial EEPROM configuration. TVME8240 User Manual Issue 1.2.9 Page 42 of 70... -
Page 43: Pci9030 Configuration Eeprom
0x0000 0x3C Local 0x16 MSW Local Space 0 Remap LAS0BA[31:16] 0x0800 0x3E Local 0x14 LSW Local Space 0 Remap LAS0BA[15:0] 0x0001 0x40 Local 0x1A MSW Local Space 1 Remap LAS1BA[31:16] 0x0400 TVME8240 User Manual Issue 1.2.9 Page 43 of 70... -
Page 44: Table 9-3 : Pci9030 Configuration Eeprom Settings
LSW Power Management Data Select 0x0000 0x84 Local 0x76 MSW Power Management Data Scale 0x0000 0x86 Local 0x74 LSW Power Management Data Scale 0x0000 Table 8-3 : PCI9030 Configuration EEPROM Settings TVME8240 User Manual Issue 1.2.9 Page 44 of 70... -
Page 45: Ip Interface
The IP FPGA also provides the IP Interface Control Registers. The IP FPGA is configured at power-up or board reset by an on board serial PROM. Board Initialization software should verify successful FPGA configuration in the Utility Status Register. TVME8240 User Manual Issue 1.2.9 Page 45 of 70... -
Page 46: Pci9030 Local Space Assignment
IP B CONTROL 0x06 IP C CONTROL 0x08 IP D CONTROL 0x0A RESET 0x0C STATUS 0x0E Reserved 0x10 - 0xFF Reserved Table 8-6 : Local Space 0 Address Map (IP Interface Register) TVME8240 User Manual Issue 1.2.9 Page 46 of 70... -
Page 47: Ip Interface Register
The Revision ID Register shows the revision of the on board IP FPGA logic. Name Description (MSB) Read : Undefined Write : No Effect Read: FPGA Logic Revision ID REV_ID Write : No Effect (LSB) Table 8-7 : Revision ID Register TVME8240 User Manual Issue 1.2.9 Page 47 of 70... -
Page 48: Ip X Control Registers
If IP recover time is enabled for an IP slot, an IP cycle for this slot will not begin until the IP recover time is expired. The IP recover time is app. 1µs. TVME8240 User Manual Issue 1.2.9 Page 48 of 70... -
Page 49: Reset Register
Write : (LSB) 0 : No Effect 1 : Assert IP RESET# Signal (Automatic Negation) Table 8-9 : Reset Register The IP RESET# signal is also asserted at power-up or board reset. TVME8240 User Manual Issue 1.2.9 Page 49 of 70... -
Page 50: Status Register
0 : No Error on IP_C ERR_C 1 : IP_C ERROR# Signal Asserted Write : No Effect Read : 0 : No Error on IP_B ERR_B 1 : IP_B ERROR# Signal Asserted Write : No Effect TVME8240 User Manual Issue 1.2.9 Page 50 of 70... - Page 51 0 : No Interrupt 1 Request on IP_A 1 : Active IP_A Interrupt 1 Request INT1_A Write : 0 : No Effect 1 : Clear Edge Sensitive IP_A Interrupt 1 Status TVME8240 User Manual Issue 1.2.9 Page 51 of 70...
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Page 52: Local Space 1 Address Map
Table 8-11 : Local Space 1 Address Map (IP A-D ID, INT, I/O Space) The TVME8240 will perform write cycles to the IP ID space. Any access to the IP INT space will assert the IP INTSEL# signal on the selected IP slot. The TVME8240 will perform write cycles to the IP INT space. -
Page 53: Local Space 2 Address Map
Table 8-13 : Local Space 3 Address Map (IP A-D Memory Space 8 bit) The 8 bit IP Memory space should be used for memory space linear byte addressing of IP modules that use IP data lines D7:0 only. TVME8240 User Manual Issue 1.2.9 Page 53 of 70... -
Page 54: Ip Interrupts
Upon detecting EPIC Serial Interrupt No. 4 read the IP Status Register to determine the IP interrupt source. Timeout interrupts and edge sensitive IP interrupts must be cleared in the IP Status Register. Error interrupts should be disabled after being noticed once. TVME8240 User Manual Issue 1.2.9 Page 54 of 70... -
Page 55: Board I/O
9 Board I/O 9.1 Board I/O Overview Figure 9-1 : Board I/O Overview TVME8240 User Manual Issue 1.2.9 Page 55 of 70... -
Page 56: Jumper
Table 9-2 : VME System Controller Jumper The VME system controller jumper controls the Universe-II BGIN3# input signal, which the Universe-II samples at the end of VME SYSRST# to determine VME System Controller mode. TVME8240 User Manual Issue 1.2.9 Page 56 of 70... -
Page 57: Leds
The ACT (Activity) LED (Green) is set by hardware control if there is any activity on the Local Memory bus or PCI bus. 9.3.4 SYS LED The SYS (System Controller) LED (Green) is set by hardware control if the Universe (VME-PCI Bridge) is the VME bus System Controller. TVME8240 User Manual Issue 1.2.9 Page 57 of 70... -
Page 58: Switches
A board reset will perform a general board hardware reset, re-configuration of the IP FPGA, PCI reset and CPU reset. If the TVME8240 is the VME bus system controller, a board reset will also trigger a VME bus system reset. -
Page 59: Connectors
VME_AM4 VME_A15 VME_A7 VME_IRQ7# VME_A14 VME_A6 VME_IRQ6# VME_A13 VME_A5 VME_IRQ5# VME_A12 VME_A4 VME_IRQ4# VME_A11 VME_A3 VME_IRQ3# VME_A10 VME_A2 VME_IRQ2# VME_A9 VME_A1 VME_IRQ1# VME_A8 -12V +12V Table 9-3 : VME P1 Connector TVME8240 User Manual Issue 1.2.9 Page 59 of 70... -
Page 60: Vme P2 Connector
SER_DCDA (i) Table 9-4 : VME P2 Connector The serial port signals (SER_x) are shown in the TVME8240 pin function. E.g. for serial port A the external TXD line must be connected to pin C28 (SER_RXDA), NOT to pin C27 (SER_TXDA). -
Page 61: Ip Interface Connectors
9.5.2.2 IP P2 Connector For each IP slot the IP P2 connector signals (IP module I/O lines) are routed directly to the appropriate pins of the 50P IP I/O ribbon cable connector. TVME8240 User Manual Issue 1.2.9 Page 61 of 70... -
Page 62: Pci Expansion Connector
C/BE1# C/BE0# C/BE3# C/BE2# AD11 AD10 AD13 AD12 AD15 AD14 AD17 AD16 AD19 AD18 AD21 AD20 AD23 AD22 AD25 AD24 AD27 AD26 AD29 AD28 AD31 AD30 PAR64 C/BE5# C/BE4# C/BE7# C/BE6# TVME8240 User Manual Issue 1.2.9 Page 62 of 70... - Page 63 AD46 AD49 AD48 AD51 AD50 AD53 AD52 AD55 AD54 AD57 AD56 AD59 AD58 AD61 AD60 AD63 AD62 Table 9-6 : PCI Expansion Connector The PCI Expansion Connector type is AMP 2-767004-4. TVME8240 User Manual Issue 1.2.9 Page 63 of 70...
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Page 64: Serial Interface Connectors
RTS (output) CTS (input) RI (input) Table 9-7 : Serial Port A DB9 male Connector 9.5.4.2 Serial Port B RS232 Adapter (TVME8240-A1-10) The RS232 adapter card (TVME824-A1-10) will be delivered with every TVME8240 board. Signal Reserved RXD (input) TXD (output) Reserved... -
Page 65: Lan Interface Connector
Table 9-9 : Serial Port B DB9 male Connector (RS422) The serial port signals are shown in the TVME8240 pin function. E.g. for serial port A the external TXD line must be connected to pin 2 (RXD input) of the serial port A connector, not to pin 3 (TXD output). -
Page 66: Installation And Use Notes
10 Installation and Use Notes 10.1 NVRAM Real-Time Clock Control The TVME8240 provides a M48T59 NVRAM / RTC device with a snaphat battery plugged on top. The snaphat battery provides power for the SRAM cells when the main power supply is off. -
Page 67: Technical Information
VME Bus Error Interrupt 11.5 Ethernet Interface • Intel 21143TD Controller • PCI DMA support • 10Base-T, 100Base-TX Interface on RJ-45 front panel connector • 10Base-T / 10Base2 AUI Port on VME P2 connector TVME8240 User Manual Issue 1.2.9 Page 67 of 70... -
Page 68: Asynchronous Serial Interface
Supports Motorola PMC-Span, TEWS’ IP-Span (TVME230) 11.8 Power Requirements The TVME8240 uses the +5V, +12V and -12V power supply pins available on the VME P1 and P2 connectors as the main power supply. The TVME8240 +3.3V board power supply is generated on board (using the VME +5V power supply). -
Page 69: Industrypack Interface
Clock rate : 8 MHz / 32 MHz selectable for each IP slot 11.9.2 I/O Interface • Four 50-pin planar connectors for ribbon cable front I/O • 1A max continuous dc current per IP I/O line TVME8240 User Manual Issue 1.2.9 Page 69 of 70... -
Page 70: Physical Data
5% to 90% (non-condensing) 11.10.5 Form Factor • Standard one slot 6U VME • 3-row (a, b, c) VME P1 & P2 connectors (PCI expansion board occupies an additional VME slot if installed) TVME8240 User Manual Issue 1.2.9 Page 70 of 70...
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