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Tews Technologies TVME8300 User Manual

Single board computer with industrypack interface (vme64x ip back i/o)
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The Embedded I/O Company
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
www.tews.com
TVME8300
Single Board Computer
with IndustryPack
(VME64x IP Back I/O)
Version 1.0

User Manual

Issue 1.4
September 2006
Phone: +49-(0)4101-4058-0
Fax: +49-(0)4101-4058-19
e-mail: info@tews.com
®
Interface
TEWS TECHNOLOGIES LLC
9190 Double Diamond Parkway,
Suite 127, Reno, NV 89521, USA
www.tews.com
Phone: +1 (775) 850 5830
Fax: +1 (775) 201 0347
e-mail: usasales@tews.com

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Summary of Contents for Tews Technologies TVME8300

  • Page 1: User Manual

    IndustryPack Interface (VME64x IP Back I/O) Version 1.0 User Manual Issue 1.4 September 2006 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 Phone: +49-(0)4101-4058-0 9190 Double Diamond Parkway, Phone: +1 (775) 850 5830 25469 Halstenbek, Germany Fax: +49-(0)4101-4058-19...
  • Page 2 MPC8245 300 MHz, 64 MB SDRAM, 8 MB in this document at any time without notice. FLASH, Fast Ethernet, VME64x IP Back I/O TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein.
  • Page 3 Added “Installation and Use Notes” section / Corrected Memory Flash first instruction offset / Added Memory Flash Types / Updated January 2005 Technical Information section Ultra-2 SCSI Controller / TVME8300-11 Board Option Obsolete. June 2006 New address TEWS LLC September 2006 TVME8300 User Manual Issue 1.4...

  • Page 4: Table Of Contents

    PIC Register Settings ....................28 4.2.3.1 Global Configuration Register (GCR) ............28 4.2.3.2 Interrupt Configuration Register (ICR) ............28 4.2.3.3 Serial Interrupt Vector / Priority Registers (SVPR) ........28 4.2.4 PIC Register Programming...................28 I2C Bus............................29 4.3.1 I2C EEPROM........................29 TVME8300 User Manual Issue 1.4 Page 4 of 70...
  • Page 5 10.3 LEDs ............................57 10.3.1 ACT LED........................57 10.3.2 SYS LED........................57 10.3.3 FAIL LED ........................57 10.3.4 FUSE LED ........................57 10.3.5 LINK LED........................57 10.3.6 100M LED........................58 10.4 Switches............................58 10.4.1 RST Switch ........................58 10.4.2 ABT Switch ........................58 TVME8300 User Manual Issue 1.4 Page 5 of 70...
  • Page 6 Power Supply Requirements ..................69 12.9.3.1 +5V Supply....................69 12.9.3.2 +12V Supply....................69 12.9.3.3 -12V Supply....................69 12.10 Physical Data..........................70 12.10.1 MTBF Data ........................70 12.10.2 Temperature .........................70 12.10.3 Weight...........................70 12.10.4 Humidity........................70 12.10.5 Form Factor ........................70 TVME8300 User Manual Issue 1.4 Page 6 of 70...
  • Page 7 Table of Figures FIGURE 1-1 : FEATURES TVME8300 ......................9 FIGURE 1-2 : BLOCK DIAGRAM TVME8300....................10 FIGURE 1-3 : BOARD LAYOUT TVME8300 ....................10 FIGURE 3-1 : ADDRESS MAP – PROCESSOR VIEW ...................16 FIGURE 3-2 : SUPPORTED TRANSFER SIZES ....................16 FIGURE 3-3 : PCI ADDRESS TRANSLATION ....................17 FIGURE 3-4 : ADDRESS MAP –...
  • Page 8 FIGURE 10-10: SERIAL PORT A (RS232) (DB9 MALE CONNECTOR) ............64 FIGURE 10-11: SERIAL PORT B (RS232) (DB9 MALE CONNECTOR) ............65 FIGURE 10-12: ETHERNET CONNECTOR (8P RJ45)...................65 FIGURE 12-1 : MTBF DATA ..........................70 TVME8300 User Manual Issue 1.4 Page 8 of 70...

  • Page 9: Introduction

    1 Introduction The TVME8300 is a standard 6U VME single slot Single Board Computer (SBC) card, using the Motorola MPC8245 Integrated Host PowerPC Processor. The board provides four single IndustryPack (IP) slots (double-sized IP modules supported) running at 8 MHz or 32 MHz (programmable for each slot) with 16 bit port width. The IndustryPack I/O lines are available at the VME P2 and P0 connectors (conforming to the VME64x IP I/O Mapping).

  • Page 10: Block Diagram

    Bridge (4 IP Slots) 82551ER IP A IP B IP C IP D RJ45 10Base-T/ 100Base-TX Figure 1-2 : Block diagram TVME8300 TVME8300 TVME001TM-10 VME64 P0/P2 to 4x50 pin Flat Cable Connector IP Slot D FAIL/FUSE LED ACT/SYS LED RST Switch...

  • Page 11: Description

    • Bank 1 consists of four 1 M x16 bit on board FLASH devices providing a total of 8 Mbyte 64 bit wide Memory FLASH memory 2.2.2 SDRAM Memory The TVME8300 provides 64 Mbyte 64 bit wide SDRAM memory build with four 8 M x 16 bit SDRAM devices. 2.2.3 NVRAM / Real Time Clock The TVME8300 uses a ST M48T59 compatible device to provide 8 Kbyte of non-volatile static RAM and real time clock.

  • Page 12: 16550 Compatible Dual Uart

    2.2.4 16550 compatible Dual UART The TVME8300 uses the Exar XR16C2550 16550 compatible dual UART with a 1.8432 MHz clock- oscillator, providing two asynchronous serial ports. Please refer to the XR16C2550 manual for details. 2.2.5 Utility Registers The TVME8300 provides some additional registers for board control and status functions.

  • Page 13: Vme Bus Interface

    VME Bus Interface The TVME8300 uses the Tundra Universe-II VME / PCI Bridge for the VME bus interface. The Universe-II VME / PCI Bridge provides a 32 bit address / 32 bit data VME bus interface. Please refer to the Universe-II documentation for details.

  • Page 14: Asynchronous Serial Interface

    Asynchronous Serial Interface The TVME8300 provides two asynchronous RS232 serial interface ports used with the on board Dual UART. Both serial ports are available on DB9 male connectors on the TVME8300 front panel. Interrupt Controller The TVME8300 uses the MPC8245 Programmable Interrupt Controller (PIC) in the serial mode for all on board interrupt sources.

  • Page 15: Status Indicators (Leds)

    2.10 Status Indicators (LEDs) The TVME8300 provides six LED status indicators visible on the TVME8300 front panel. The following LED indicators are available: • VME Bus System Controller (Green) • Board Activity (Green) • Board Failure (Red) • Fuse Status (Red) •...

  • Page 16: Address Maps

    Figure 3-1 : Address Map – Processor View Device Read Write SDRAM Memory FLASH 64 bit Only Peripheral Devices 8 bit Only 8 bit Only Boot FLASH 8 bit Only Figure 3-2 : Supported Transfer Sizes TVME8300 User Manual Issue 1.4 Page 16 of 70...

  • Page 17: Address Map - Pci Memory Master View

    Boot FLASH (8 bit wide) Figure 3-4 : Address Map – PCI Memory Master View On the TVME8300 the MPC8245 responds as a target to PCI Memory cycles for accessing SDRAM, PCI accessible MPC8245 EUMB, Memory FLASH, Peripheral Devices and Boot FLASH.

  • Page 18: Address Map - Pci I/O Master View

    For read or write accesses to the Peripheral Devices only 8 bit (byte) transfer sizes are allowed. For the NVRAM / RTC register map please refer to the M48T59 device documentation. For the UART register map please refer to the XR16C2550 documentation. TVME8300 User Manual Issue 1.4 Page 18 of 70...

  • Page 19: Address Map - Utility Register Detail

    0: Boot FLASH Writes Disabled 1: Boot FLASH Writes Enabled 0: Fuse Interrupt Disabled FUSE_INT_EN 1: Fuse Interrupt Enabled Write as '0' Reserved Undefined for Reads (LSB) Figure 3-8 : Control Register TVME8300 User Manual Issue 1.4 Page 19 of 70...

  • Page 20: Status Register

    1: Active User Interrupt Read : 0: No Fuse Interrupt FUSE_INT 1: Active Fuse Interrupt Write ‘1’ to clear interrupt Write as '0' Reserved Undefined for Reads (LSB) Figure 3-10: Interrupt Register TVME8300 User Manual Issue 1.4 Page 20 of 70...

  • Page 21: Led Register

    1: Jumper 1 Closed 0: Jumper 2 Open JMP_2 1: Jumper 2 Closed 0: Jumper 3 Open JMP_3 1: Jumper 3 Closed Reserved Undefined for Reads (LSB) Figure 3-12: Jumper Register TVME8300 User Manual Issue 1.4 Page 21 of 70...

  • Page 22: Fuse Register

    If a fuse interrupt occurs, this should be indicated to the system and the fuse interrupt should be disabled (otherwise there may be permanent fuse interrupts as long as the overload situation exists). TVME8300 User Manual Issue 1.4 Page 22 of 70...

  • Page 23: Mpc8245

    Configuration Register settings are shown in little endian order. Since on the TVME8300 the MPC8245 processor and peripheral logic operates in big endian mode, software must either use byte reversed load / store instructions or byte-swap the values for the CONFIG_ADDR and CONFIG_DATA port access.

  • Page 24: Configuration Register Settings

    0x72 0x20 Configuration Register 2 Output Driver Control 0x73 0xD5 Register Clock Driver Control 0x74 0x0000 Register 0x76 Misc. I/O Control Register 1 0x00 0x77 Misc. I/O Control Register 2 0x30 TVME8300 User Manual Issue 1.4 Page 24 of 70...
  • Page 25 Extended ROM 0xDC reset_default Configuration Register 4 Address Map B Options Register 0xE0 0xC0 (AMBOR) 0xE2 PLL Configuration Register 0x08 Memory Control 0xF0 Configuration Register 1 0x03E8_0000 (MCCR1) 0xF4 0x0A40_1820 Memory Control TVME8300 User Manual Issue 1.4 Page 25 of 70...

  • Page 26: Figure 4-1 : Mpc8245 Configuration Register Settings

    The MEMGO bit in the MCCR1 register (offset 0xF0) must not be set until all other memory configuration parameters have been appropriately configured. The DLL_RESET bit in the AMBOR register (offset 0xE0) must be explicitly set and then cleared by software during initialization. TVME8300 User Manual Issue 1.4 Page 26 of 70...

  • Page 27: Programmable Interrupt Controller (Pic)

    Programmable Interrupt Controller (PIC) The TVME8300 uses the MPC8245 Programmable Interrupt Controller (PIC) in serial mode as the board interrupt controller. 4.2.1 PIC Serial Interrupt Assignment The following interrupt sources are available and mapped to the PIC serial interrupt channel:...

  • Page 28: Pic Register Access

    The PIC Registers are part of the MPC8245 Embedded Utility Memory Block (EUMB). The EUMB base address is set in the EUMBBAR Register. For the TVME8300 memory map the EUMB base address is set to 0xFCF0_0000. 4.2.3 PIC Register Settings 4.2.3.1...

  • Page 29: I2C Bus

    I2C Bus The TVME8300 provides an on board I2C EEPROM for board specific data. 4.3.1 I2C EEPROM EEPROM Description Content Offset 0x00 Check sum See note below 0x01 Number Of Valid Bytes Following e.g. 0x06 0x02 Board Type (High Byte)

  • Page 30: Flash Programming

    5 FLASH Programming 8 bit Wide Socket Boot FLASH The TVME8300 provides 1 MByte of 8 bit wide socket Boot FLASH using two 512 K x 8 bit 32-pin PLCC FLASH devices. The Boot FLASH address range is 0xFFF0_0000 to 0xFFFF_FFFF.

  • Page 31: Figure 5-2 : Boot Flash Auto Select Codes

    SA10 0xFFFA_0000 - 0xFFFA_FFFF SA11 0xFFFB_0000 - 0xFFFB_FFFF SA12 0xFFFC_0000 - 0xFFFC_FFFF SA13 0xFFFD_0000 - 0xFFFD_FFFF SA14 0xFFFE_0000 - 0xFFFE_FFFF SA15 0xFFFF_0000 - 0xFFFF_FFFF Figure 5-3 : Boot FLASH Sector Map TVME8300 User Manual Issue 1.4 Page 31 of 70...

  • Page 32: Bit Wide On Board Memory Flash

    64 bit Wide On Board Memory FLASH The TVME8300 provides 8 Mbyte of 64 bit wide board mounted Memory FLASH using four 1 M x 16 bit FLASH devices. The Memory FLASH address range is 0xFF00_0000 to 0xFF7F_FFFF. For writes to the Memory FLASH double-word (64 bit) transfer sizes must be used.

  • Page 33: Figure 5-4 : Memory Flash Command Cycles

    Cmd.- #Cyc Seq. Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read Reset Auto Select Write Chip Erase Sector Erase Figure 5-4 : Memory FLASH Command Cycles TVME8300 User Manual Issue 1.4 Page 33 of 70...

  • Page 34: Figure 5-5 : Memory Flash Auto Select Codes

    SST 39xF160x (Uniform) 0xFF00_0000 - 0xFF00_3FFF 0xFF00_4000 - 0xFF00_7FFF 0xFF00_8000 - 0xFF00_BFFF 0xFF00_C000 - 0xFF00_FFFF 0xFF01_0000 - 0xFF01_3FFF … … … SA511 0xFF7F_C000 - 0xFF7F_FFFF Figure 5-6 : Memory FLASH Sector Map TVME8300 User Manual Issue 1.4 Page 34 of 70...

  • Page 35: Vme Bus Interface

    The Tundra Universe-II VME / PCI bridge is used as the TVME8300 VME / PCI bridge. The Universe-II is accessible on both the VME bus and the TVME8300 PCI bus (device number 13). Please refer to the Universe-II manual for a detailed description of the Universe-II VME / PCI bridge.

  • Page 36: Universe-Ii Reset Signals

    If the Universe-II is not the VME bus System Controller, a VME bus System Reset will also trigger a TVME8300 board reset (using the Universe-II LRST# output). The Universe-II VRSYSRST# and VXSYSRST# signals are mapped to the VME bus SYSRST# signal.

  • Page 37: Ethernet Interface

    7 Ethernet Interface The Intel 82551ER Fast Ethernet Controller is used for the TVME8300 Ethernet interface. The 82551ER is accessible on the TVME8300 PCI bus (device number 14). The 82551ER INT# interrupt output is mapped to serial channel no. 2 of the MPC8245 PIC.

  • Page 38: 82551Er Configuration Eeprom

    Tbd. Reserved 0x10 - 0x3E 0xFFFF EEPROM Checksum 0x3F variant Figure 7-2 : 82551ER Configuration EEPROM Settings Media Capabilities IEEE 802.3 10Base-T / 100Base-TX interface on the RJ45 front panel connector. TVME8300 User Manual Issue 1.4 Page 38 of 70...

  • Page 39: Ip Interface

    IP interface. PCI9030 PCI Target Chip The PCI9030 provides four local spaces 0:3 that are used for accessing the TVME8300 IP interface. The PCI9030 is accessible on the TVME8300 PCI bus (device number 16). The PCI9030 INT# interrupt output is mapped to serial channel no. 4 of the MPC8245 PIC.

  • Page 40: Pci9030 Pci Header

    HS CSR HS NxtCap HS CapID 0x0000_0006 0x4C VPD Address VPD NxtCap VPD CapID 0x0000_0003 0x50 VPD Data 0x0000_0000 Read back Value after writing all 1's. Figure 8-1 : PCI9030 PCI Header TVME8300 User Manual Issue 1.4 Page 40 of 70...

  • Page 41: Local Configuration Register

    Serial EEPROM / Interrupt Control & Status 0x0030_0049 INTCSR 0x50 Miscellaneous CNTRL 0x007A_4000 0x54 General Purpose I/O GPIOC 0x0224_9251 Figure 8-2 : PCI9030 Local Configuration Register Shown values are register values after serial EEPROM configuration. TVME8300 User Manual Issue 1.4 Page 41 of 70...

  • Page 42: Pci9030 Configuration Eeprom

    0x0800 0x3E Local 0x14 LSW Local Space 0 Remap LAS0BA[15:0] 0x0001 0x40 Local 0x1A MSW Local Space 1 Remap LAS1BA[31:16] 0x0400 0x42 Local 0x18 LSW Local Space 1 Remap LAS1BA[31:16] 0x0001 TVME8300 User Manual Issue 1.4 Page 42 of 70...

  • Page 43: Figure 8-3 : Pci9030 Configuration Eeprom Settings

    LSW Power Management Data Select 0x0000 0x84 Local 0x76 MSW Power Management Data Scale 0x0000 0x86 Local 0x74 LSW Power Management Data Scale 0x0000 Figure 8-3 : PCI9030 Configuration EEPROM Settings TVME8300 User Manual Issue 1.4 Page 43 of 70...

  • Page 44: Ip Interface

    Control & Status Registers. The IP FPGA logic is configured at power-up or board reset by an on board serial PROM. Board Initialization software should verify successful FPGA configuration in the Utility Status Register. TVME8300 User Manual Issue 1.4 Page 44 of 70...

  • Page 45: Pci9030 Local Space Assignment

    IP B CONTROL 0x06 IP C CONTROL 0x08 IP D CONTROL 0x0A RESET 0x0C STATUS 0x0E Reserved 0x10 - 0xFF Reserved Figure 8-6 : Local Space 0 Address Map (IP Interface Register) TVME8300 User Manual Issue 1.4 Page 45 of 70...

  • Page 46: Ip Interface Register

    The Revision ID Register indicates the revision of the on board IP FPGA logic. Name Description (MSB) Read Only REV_ID FPGA Logic Revision ID (LSB) Figure 8-7 : Revision ID Register TVME8300 User Manual Issue 1.4 Page 46 of 70...

  • Page 47: Ip Control Registers

    If IP recover time is enabled for an IP slot, an IP cycle for this slot will not begin until the IP recover time is expired after the previous IP access. The IP recover time is app. 1µs. TVME8300 User Manual Issue 1.4 Page 47 of 70...

  • Page 48: Reset Register

    Asserting IP reset by software does not reset the clock mode to 8 MHz. If 32 MHz clock mode is used, the clock mode should be reset to 8 MHz prior to asserting the IP reset by software. TVME8300 User Manual Issue 1.4 Page 48 of 70...

  • Page 49: Status Register

    Write ‘1’ to clear Edge Sensitive IP_D Interrupt 0 Status Read : 0 : No Interrupt 1 Request on IP_C INT1_C 1 : Active IP_C Interrupt 1 Request Write ‘1’ to clear Edge Sensitive IP_C Interrupt 1 Status TVME8300 User Manual Issue 1.4 Page 49 of 70...

  • Page 50: Figure 8-10: Status Register

    An IP timeout occurs if the IP module fails to generate the IP ACK# signal within the IP timeout time. An IP timeout is not reported to the PCI9030 or the PCI Master, but is reported in the Status Register. For timed-out reads all F's are returned. TVME8300 User Manual Issue 1.4 Page 50 of 70...

  • Page 51: Local Space 1 Address Map

    Figure 8-11: Local Space 1 Address Map (IP A-D ID, INT, I/O Space) The TVME8300 will perform write cycles to the IP ID space. Any access to the IP INT space will assert the IP INTSEL# signal on the selected IP slot. The TVME8300 will perform write cycles to the IP INT space.

  • Page 52: Local Space 2 Address Map

    Figure 8-13: Local Space 3 Address Map (IP A-D Memory Space 8 bit) The 8 bit IP Memory space should be used for memory space incremental byte addressing of IP modules that use IP data lines D[7:0] only. TVME8300 User Manual Issue 1.4 Page 52 of 70...

  • Page 53: Ip Interrupts

    If the IP module does hold the asserted ERROR# signal level, but does not provide an acknowledge mechanism, the ERROR# interrupt should be disabled when entered for the first time. TVME8300 User Manual Issue 1.4 Page 53 of 70...

  • Page 54: Pci Bus Overview

    9 PCI Bus Overview Figure 9-1: PCI Bus Overview TVME8300 User Manual Issue 1.4 Page 54 of 70...

  • Page 55: Board I/O

    ACT/SYS LED RST Switch IP Slot C ABT Switch LINK/100M LED IP Slot B IP Slot A PCI Expansion PLD JTAG CPU JTAG 0 1 2 3 Figure 10-1: Board I/O Overview TVME8300 User Manual Issue 1.4 Page 55 of 70...

  • Page 56: Jumper

    Universe-II samples at power-up to determine VME System Controller mode. 10.2.3 User Jumper The TVME8300 provides four user defined jumpers. The status of the four user jumpers can be read in the Utility User Jumper Status Register. TVME8300 User Manual Issue 1.4...

  • Page 57: Leds

    Label Color Description Indicates Memory Bus or Board Activity Green PCI Bus activity VME Bus System Indicates if the TVME8300 is configured as Green Controller VME Bus System Controller Board Failure FAIL User controlled Status LED Indicates triggered fuses for...

  • Page 58: 100M Led

    The ABT (ABORT) switch can be used to generate a CPU interrupt. The Abort Switch is mapped to serial interrupt no. 1 of the MPC8245 PIC. Serial interrupt no. 1 must be configured as edge sensitive. TVME8300 User Manual Issue 1.4 Page 58 of 70...

  • Page 59: Connectors

    VME_IRQ7# VME_A14 VME_3.3V VME_A6 VME_IRQ6# VME_A13 VME_A5 VME_IRQ5# VME_A12 VME_3.3V VME_A4 VME_IRQ4# VME_A11 VME_A3 VME_IRQ3# VME_A10 VME_3.3V VME_A2 VME_IRQ2# VME_A9 VME_A1 VME_IRQ1# VME_A8 VME_3.3V -12V +12V Figure 10-5: VME P1 Connector TVME8300 User Manual Issue 1.4 Page 59 of 70...

  • Page 60: Vme P0 Connector

    IP_C_IO_20 IP_C_IO_21 IP_C_IO_22 IP_C_IO_23 IP_C_IO_24 IP_C_IO_25 IP_C_IO_26 IP_C_IO_27 IP_C_IO_28 IP_C_IO_29 IP_C_IO_30 IP_C_IO_31 IP_C_IO_32 IP_C_IO_33 IP_C_IO_34 IP_C_IO_35 IP_C_IO_36 IP_C_IO_37 IP_C_IO_38 IP_C_IO_39 IP_C_IO_40 IP_C_IO_41 IP_C_IO_42 IP_C_IO_43 IP_C_IO_44 IP_C_IO_45 Figure 10-6: VME P0 Connector TVME8300 User Manual Issue 1.4 Page 60 of 70...

  • Page 61: Vme P2 Connector

    IP_B_IO_33 IP_A_IO_41 VME_D27 IP_A_IO_42 IP_B_IO_34 IP_B_IO_35 IP_A_IO_43 VME_D28 IP_A_IO_44 IP_B_IO_36 IP_A_IO_45 VME_D29 IP_A_IO_46 IP_B_IO_37 IP_B_IO_38 IP_A_IO_47 VME_D30 IP_A_IO_48 IP_B_IO_39 IP_A_IO_49 VME_D31 IP_A_IO_50 IP_B_IO_40 VME_3.3V VME_3.3V VME_3.3V Figure 10-7: VME P2 Connector TVME8300 User Manual Issue 1.4 Page 61 of 70...

  • Page 62: Ip Interface Connectors

    The following signals have an on board pull-up resistor (4K7, 3.3V): RESET#, WRITE#, IDSEL#, IOSEL#, INTSEL#, MEMSEL#, ACK#, INTREQ0#, INTREQ1#, ERROR#, STROBE#, RSV0, RSV1, DMAREQ0#, DMAREQ1#, DMAACK#, DMAEND#. DMA is not supported on the TVME8300 IP interface. 10.5.2.2 IP P2 Connector For each IP slot the IP P2 connector signals (IP module I/O lines) are routed directly to the appropriate pins on the VME P2 and VME P0 connectors (conforming to the VME64x IP I/O mapping).

  • Page 63: Pci Expansion Connector

    STOP# FRAME# ACK64# REQ64# RST# C/BE1# C/BE0# C/BE3# C/BE2# AD11 AD10 AD13 AD12 AD15 AD14 AD17 AD16 AD19 AD18 AD21 AD20 AD23 AD22 AD25 AD24 AD27 AD26 AD29 AD28 AD31 AD30 TVME8300 User Manual Issue 1.4 Page 63 of 70...

  • Page 64: Serial Interface Connectors

    RS232 RI (input) RS232 Figure 10-10: Serial Port A (RS232) (DB9 Male Connector) 10.5.4.2 Serial Port B Signal Level DCD (input) RS232 RXD (input) RS232 TXD (output) RS232 DTR (output) RS232 TVME8300 User Manual Issue 1.4 Page 64 of 70...

  • Page 65: Ethernet Interface Connector

    RS232 Figure 10-11: Serial Port B (RS232) (DB9 Male Connector) The serial port signals are shown in the TVME8300 pin function. E.g. the TXD output line of the external device must be connected to pin 2 (RXD input) of the serial port connector, not to pin 3 (TXD output).

  • Page 66: Installation And Use Notes

    11 Installation and Use Notes 11.1 NVRAM Real-Time Clock Control The TVME8300 provides a M48T59 NVRAM / RTC device with a snaphat battery plugged on top. The snaphat battery provides power for the SRAM cells when the main power supply is off.

  • Page 67: Technical Information

    System Controller Jumper (Yes, No, Auto Detect) • Four Location Monitors • DMA Controller 12.5 Ethernet Interface • Intel 82551ER Controller • PCI DMA support • 10Base-T / 100Base-TX Interface on RJ-45 front panel connector TVME8300 User Manual Issue 1.4 Page 67 of 70...

  • Page 68: Asynchronous Serial Interface

    12.9.1 Power Supply Scheme The TVME8300 uses the +5V, +12V and -12V power supply pins available on the VME P1 and P2 connectors as the main power supply. The TVME8300 +3.3V power supply and other power supply voltages are derived from the +5V power supply on board.

  • Page 69: Power Supply Requirements

    Available on all IP slots, max 1A per IP slot (limited by number of -12V pins on IP connector), max 2A total for all IP slots (IP slots A – D fused for a total of 2A) TVME8300 User Manual Issue 1.4 Page 69 of 70...

  • Page 70: Physical Data

    • One slot 6U VME • 5-row (z, a, b, c, d) VME P1 & P2 connectors + VME64x P0 connector (PCI expansion board occupies an additional VME slot if installed) TVME8300 User Manual Issue 1.4 Page 70 of 70...

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