Table of Contents
Advertisement
Quick Links
The Embedded I/O Company
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
www.tews.com
TVME8240A
Single Board Computer
with IndustryPack
Version 2.0
User Manual
Issue 1.1
May 2008
Phone: +49-(0)4101-4058-0
Fax: +49-(0)4101-4058-19
e-mail: info@tews.com
®
Interface
TEWS TECHNOLOGIES LLC
9190 Double Diamond Parkway,
Suite 127, Reno, NV 89521, USA
www.tews.com
Phone: +1 (775) 850 5830
Fax: +1 (775) 201 0347
e-mail: usasales@tews.com
Advertisement
Table of Contents
Subscribe to Our Youtube Channel
Related Manuals for Tews Technologies TVME8240A
Summary of Contents for Tews Technologies TVME8240A
- Page 1 Single Board Computer ® with IndustryPack Interface Version 2.0 User Manual Issue 1.1 May 2008 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 Phone: +49-(0)4101-4058-0 9190 Double Diamond Parkway, Phone: +1 (775) 850 5830 25469 Halstenbek, Germany Fax: +49-(0)4101-4058-19...
- Page 2 MPC8245 300 MHz, 64 MB SDRAM, document at any time without notice. 2 + 8 MB Flash, Fast Ethernet, Front Panel I/O TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the TMVE8240A-12 device described herein.
- Page 3 Issue Description Date Preliminary Issue for TVME8240A V2.0 Major board version change. Product ID changed to TVME820A. March 2007 MPC8245 CPU, 2x 82551 Ethernet Controller, 32 KB NVRAM, VME Bus Error Interrupt, extended Boot Flash, readable switch, remote control & status, extended...
-
Page 4: Table Of Contents
PIC Register Settings ....................30 4.2.2.1 Global Configuration Register (GCR) ............30 4.2.2.2 PIC Interrupt Configuration Register (EICR)..........31 4.2.2.3 Serial Interrupt Vector / Priority Registers (SVPR) ........31 4.2.2.4 PIC Register Programming ................31 I2C EEPROM ..........................32 TVME8240A User Manual Issue 1.1 Page 4 of 96... - Page 5 16 bit SCSI Targets on the VME P2 8 bit SCSI interface..........62 IP BUS INTERFACE....................63 PCI9030 PCI Target Chip ......................63 9.1.1 PCI9030 PCI Header....................64 9.1.2 Local Configuration Register ..................65 9.1.3 PCI9030 Configuration EEPROM ................66 TVME8240A User Manual Issue 1.1 Page 5 of 96...
- Page 6 IP Interrupts ..........................76 PCI DEVICE SUMMARY ..................77 BOARD I/O ....................... 78 11.1 Board I/O Overview ........................78 11.2 Jumper ............................79 11.2.1 SCSI Termination Jumper (TVME8240A-12/-22 only) ..........79 11.2.2 Boot Select Jumper ......................80 11.2.3 VME System Controller Jumper ...................80 11.3 Header ............................81 11.3.1...
- Page 7 TECHNICAL INFORMATION ................... 93 13.1 Processor............................93 13.2 Memory ............................93 13.3 VME Interface ..........................93 13.4 Ethernet Interface ........................93 13.5 SCSI Interface (TVME8240A-12/-22 only).................93 13.6 Asynchronous Serial Interface ....................94 13.7 PCI Expansion Connector......................94 13.8 IndustryPack Interface ......................94 13.8.1 Logic Interface ......................94 13.8.2 I/O Interface ........................94...
- Page 8 Table of Figures FIGURE 1-1 : FEATURES TVME8240A ......................11 FIGURE 1-2 : TVME8240A BLOCK DIAGRAM ....................12 FIGURE 1-3 : TVME8240A BOARD VIEW ......................13 FIGURE 2-1 : STATUS INDICATORS ......................17 FIGURE 3-1 : ADDRESS MAP – PROCESSOR VIEW ...................19 FIGURE 3-2 : SUPPORTED TRANSFER SIZES ....................20 FIGURE 3-3 : PCI ADDRESS TRANSLATION ....................20...
- Page 9 FIGURE 11-6 : REMOTE FRONT HEADER....................81 FIGURE 11-7 : REMOTE CONNECTION EXAMPLE..................81 FIGURE 11-8 : LED OVERVIEW ........................82 FIGURE 11-9 : VME P1 CONNECTOR ......................84 FIGURE 11-10 : VME P2 CONNECTOR ......................85 TVME8240A User Manual Issue 1.1 Page 9 of 96...
- Page 10 FIGURE 11-14 : SERIAL PORT 1 DB9 MALE CONNECTOR.................90 FIGURE 11-15 : SERIAL PORT 2 DB9 MALE CONNECTOR.................90 FIGURE 11-16 : LAN RJ45 CONNECTOR ......................91 FIGURE 13-1 : MTBF DATA ..........................96 FIGURE 13-2 : WEIGHT DATA........................96 TVME8240A User Manual Issue 1.1 Page 10 of 96...
-
Page 11: Introduction
1 Introduction The TVME8240A is a VME single slot Single Board Computer (SBC) using the Motorola MPC8245 Embedded PowerPC Processor. The TVME8240A provides four single IndustryPack (IP) slots supporting single and double-sized IP modules running at 8 MHz or 32 MHz. There is a front-I/O ribbon cable connector for each IP Slot. -
Page 12: Block Diagram
16 bit Ultra SCSI 100BaseTX 50 pin 50 pin 50 pin 50 pin 8 bit Ultra SCSI 4 x 50 pin Flat Cable Connector 100Base-TX Figure 1-2 : TVME8240A Block Diagram TVME8240A User Manual Issue 1.1 Page 12 of 96... -
Page 13: Figure 1-3 : Tvme8240A Board View
Abort Switch LAN 1 IP Slot C VME P2 SCSI (SCSI, COM, LAN 2, IP Slot D REMOTE) REMOTE XILINX MPC8245 PCI Expansion Connector JTAG COP/JTAG Figure 1-3 : TVME8240A Board View TVME8240A User Manual Issue 1.1 Page 13 of 96... -
Page 14: Description
64 bit wide Application Flash Memory. 2.2.2 SDRAM Memory The TVME8240A-1x provides four 8 M x 16 bit SDRAM devices, building a total of 64 Mbyte, 64 bit wide SDRAM memory. The TVME8240A-2x provides four 32 M x 16 bit SDRAM devices, building a total of 256 Mbyte, 64 bit wide SDRAM memory. -
Page 15: Nvram / Real-Time Clock
2.2.3 NVRAM / Real-Time Clock The TVME8240A provides an ST M48T37 compatible device to provide 32 Kbyte of non-volatile static RAM and real-time clock. The M48T37 device consists of two parts: • A 44-pin SO device which implements the Real Time Clock and Watchdog functions plus 32 Kbyte SRAM and sockets for the Snaphat battery. -
Page 16: Vme Bus Interface
Please refer to the 53C875 manuals for details. 2.7 IP Bus Interface The TVME8240A features the PCI9030 PCI Target Chip (PLX Technologies) for addressing the IndustryPack Interface on the PCI bus. A Xilinx FPGA is used for implementing the IndustryPack interface logic. -
Page 17: Asynchronous Serial Interface
Please see the MPC8245 section for details. 2.11 Status Indicators The TVME8240A provides four status indicators visible at the front panel. The four status indicators are also available on the 10-pin Remote Header and on the VME P2 connector. Function... -
Page 18: Reset Switch
The Abort switch function can also be controlled via Remote Header or VME P2 connector pins. 2.14 Remote Header The TVME8240A features a 10-pin Remote Header providing Reset and Abort switch control inputs plus status indicator outputs. These signals are also available on the VME P2 connector. -
Page 19: Address Maps
3 Address Maps The TVME8240A uses the MPC8245 address map B in host mode. The following address maps reflect MPC8245 configuration register settings done by board initialization software. 3.1 Address Map - Processor View Processor Address Size Description (Byte) Start... -
Page 20: Address Map - Pci Memory Master View
1 M – 4 K Reserved 0xFD00_0000 0xFDFF_FFFF 16 M SDRAM Memory (0-Based) 0xFE00_0000 0xFEFF_FFFF 16 M Reserved Application Flash (lower 8 Mbyte) 0xFF00_0000 0xFF7F_FFFF (64 bit wide) 0xFF80_0000 0xFFBF_FFFF Peripheral Devices (8 bit wide) TVME8240A User Manual Issue 1.1 Page 20 of 96... -
Page 21: Address Map - Pci I/O Master View
Boot Flash (8 bit wide) Figure 3-4 : Address Map – PCI Memory Master View On the TVME8240A the MPC8245 responds as a target to PCI Memory cycles for accessing SDRAM, PCI accessible MPC8245 EUMB, Application Flash, Peripheral Devices and Boot Flash. -
Page 22: Address Map - Utility Register Detail
A board reset will perform a general board hardware reset, re-configuration of the IP FPGA, PCI reset and CPU reset. If the TVME8240A is the VME bus system controller, a board reset will also trigger a VME bus system reset. -
Page 23: Status Register (0Xff90_0001)
Fuse is still triggered. This status bit is capable of generating an interrupt if enabled in the Control Register. Figure 3-9 : Status Register Board initialization software should verify successful IP FPGA configuration. TVME8240A User Manual Issue 1.1 Page 23 of 96... -
Page 24: Control Register 2 (0Xff90_0002)
Undefined for Reads Write as '0'. Reserved (LSB) Undefined for Reads Figure 3-10: Control Register 2 For RS422 Mode on Serial Channel 2 the UART MCR[1] bit (0xFFB0_0004) must be clear. TVME8240A User Manual Issue 1.1 Page 24 of 96... -
Page 25: Status Register 2 (0Xff90_0003)
Undefined for Reads Figure 3-12: FPGA Flash Programming Register This register should only be used in case of an IP FPGA logic update. It should not be used during normal operation. TVME8240A User Manual Issue 1.1 Page 25 of 96... -
Page 26: Mpc8245
4 MPC8245 The TVME8240A uses the MPC8245 in host mode with address map B in extended addressing mode. The MPC8245 processor and peripheral logic are configured to operate in big endian mode. 4.1 MPC8245 Configuration Register Setting up the MPC8245 Configuration Registers is scope of the board initialization software. -
Page 27: Configuration Register Settings
0x72 0x20 Configuration Register 2 Output Driver Control 0x73 0xDD Register Clock Driver Control 0x74 0x0000 Register 0x76 Misc. I/O Control Register 1 0x00 0x77 Misc. I/O Control Register 2 0x20 TVME8240A User Manual Issue 1.1 Page 27 of 96... - Page 28 Extended ROM 0xD4 0xB5FF_8000 Configuration Register 2 Extended ROM 0xD8 reset_default Configuration Register 3 8 Mbyte Opt.: 0x0000_000B 16 Mbyte Opt.: Extended ROM 0xDC Configuration Register 4 0x0000_000C 32 Mbyte Opt.: 0x0000_000D TVME8240A User Manual Issue 1.1 Page 28 of 96...
-
Page 29: Figure 4-1 : Mpc8245 Configuration Register Settings
The MEMGO bit in the MCCR1 register (offset 0xF0) must not be set until all other memory configuration parameters have been appropriately configured. The DLL_RESET bit in the AMBOR register (offset 0xE0) must be explicitly set and then cleared by software during initialization. TVME8240A User Manual Issue 1.1 Page 29 of 96... -
Page 30: Mpc8245 Interrupt Controller
4.2 MPC8245 Interrupt Controller The TVME8240A uses the MPC8245 PIC in serial mode as the board interrupt controller. The following table shows the available interrupt sources and the serial interrupt mapping. Serial Edge / Level Polarity Interrupt Source Interrupt No. -
Page 31: Pic Interrupt Configuration Register (Eicr)
The polarity and sense bits in the SVPRs must be configured accordingly to the PIC Serial Interrupt Assignment table. Please refer to chapter “Interrupt Controller” for the PIC serial interrupt assignment. 4.2.2.4 PIC Register Programming The PIC Programming Guidelines from the MPC8245 manual should be followed. TVME8240A User Manual Issue 1.1 Page 31 of 96... -
Page 32: I2C Eeprom
4.3 I2C EEPROM The TVME8240A provides an on board I2C EEPROM for board specific data. EEPROM Description Content Offset 0x00 Check sum see note below 0x01 Number Of Valid Bytes Following e.g. 0x06 0x02 Board Type (High Byte) 0x2030 for... -
Page 33: Flash Programming
Note: The SST Manufacturer ID for the SST Boot Flash is 0xBF. Manufacturer ID and Device ID are readable using the Auto-Select command. Figure 5-2 : Supported SST Boot Flash Types TVME8240A User Manual Issue 1.1 Page 33 of 96... -
Page 34: Sst Boot Flash Command Cycles
Sector Address Range (Byte) 0xFFE0_0000 - 0xFFE0_0FFF 0xFFE0_1000 - 0xFFE0_1FFF 0xFFE0_2000 - 0xFFE0_2FFF … … … SA510 0xFFFF_E000 - 0xFFFF_EFFF SA511 0xFFFF_F000 - 0xFFFF_FFFF Figure 5-4 : SST39VF168x Boot Flash Sector Map TVME8240A User Manual Issue 1.1 Page 34 of 96... -
Page 35: Spansion 29Gl0Xxa Flash Types
Sectors (8 Kbyte each) 0xFFC0_0000 - 4 Mbyte 0xFFFF_FFFF 63 sectors (64 Kbyte each) plus 8 Bottom S29GL032A-R4 Boot Sectors (8 Kbyte each) Figure 5-6 : Supported Spansion Boot Flash Types TVME8240A User Manual Issue 1.1 Page 35 of 96... -
Page 36: Spansion Boot Flash Command Cycles
WBL = Additional Write Buffer Location (Address must be within same Write Buffer Page as PA. Each Write-Buffer-Page has a 32 Byte address boundary). Figure 5-7 : Spansion Boot Flash Command Cycles TVME8240A User Manual Issue 1.1 Page 36 of 96... -
Page 37: Spansion Boot Flash Identifier
DQ7, DQ5 and DQ1 should be monitored to determine the device status during write buffer programming. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. TVME8240A User Manual Issue 1.1 Page 37 of 96... -
Page 38: Spansion Flash Flowcharts
5.1.2.5 Spansion Flash Flowcharts START Write Erase Command Sequence Data Poll of Erasing Embedded Bank from System Erase algorithm in progress Data = all 0xFF? Erasing Completed Figure 5-9 : Spansion Flash Erase Operation TVME8240A User Manual Issue 1.1 Page 38 of 96... -
Page 39: Figure 5-10 : Spansion Flash Write Buffer Programming
If DQ1 = 1, write the Write-Buffer-Programming-Abort-Reset command. If DQ5 = 1, write the Reset command. Figure 5-10 : Spansion Flash Write Buffer Programming TVME8240A User Manual Issue 1.1 Page 39 of 96... -
Page 40: Figure 5-11 : Spansion Flash Data Polling
VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. Figure 5-11 : Spansion Flash Data Polling TVME8240A User Manual Issue 1.1 Page 40 of 96... -
Page 41: Spansion Boot Flash Sector Maps
0xFFE0_4000 - 0xFFE0_5FFF 0xFFE0_6000 - 0xFFE0_7FFF 0xFFE0_8000 - 0xFFE0_9FFF 0xFFE0_A000 - 0xFFE0_BFFF 0xFFE0_C000 - 0xFFE0_DFFF 0xFFE0_E000 - 0xFFE0_FFFF 0xFFE1_0000 - 0xFFE1_FFFF 0xFFE2_0000 - 0xFFE2_FFFF SA10 0xFFE3_0000 - 0xFFE3_FFFF … … … TVME8240A User Manual Issue 1.1 Page 41 of 96... -
Page 42: Figure 5-13 : S29Gl016A-R2 Boot Flash Sector Map
Sector Address Range (Byte) 0xFFC0_0000 - 0xFFC0_1FFF 0xFFC0_2000 - 0xFFC0_3FFF 0xFFC0_4000 - 0xFFC0_5FFF 0xFFC0_6000 - 0xFFC0_7FFF 0xFFC0_8000 - 0xFFC0_9FFF 0xFFC0_A000 - 0xFFC0_BFFF 0xFFC0_C000 - 0xFFC0_DFFF 0xFFC0_E000 - 0xFFC0_FFFF 0xFFC1_0000 - 0xFFC1_FFFF TVME8240A User Manual Issue 1.1 Page 42 of 96... -
Page 43: Figure 5-15 : S29Gl032A-R4 Boot Flash Sector Map
0xFFC2_0000 - 0xFFC2_FFFF SA10 0xFFC3_0000 - 0xFFC3_FFFF … … … SA68 0xFFFD_0000 - 0xFFFD_FFFF SA69 0xFFFE_0000 - 0xFFFE_FFFF SA70 0xFFFF_0000 - 0xFFFF_FFFF Figure 5-15 : S29GL032A-R4 Boot Flash Sector Map TVME8240A User Manual Issue 1.1 Page 43 of 96... -
Page 44: Application Flash Memory
The 64 bit Application Flash Bank is build by using four parallel x16 Flash devices. The SST Manufacturer ID read for the Application Flash is 0x00BF_00BF_00BF_00BF. Manufacturer ID and Device ID are readable using the Auto-Select command. Figure 5-17 : Supported SST Application Flash Types TVME8240A User Manual Issue 1.1 Page 44 of 96... -
Page 45: Sst 39Vf16Xx/39Vf32Xx Application Flash Command Cycles
= 0xFFFF_FFFF_FFFF_FFFF at the Flash base address for Chip Erase or at the given sector/block address for Sector/Block Erase. Figure 5-18 : SST 39VF16xx/39VF32xx Application Flash Command Cycles TVME8240A User Manual Issue 1.1 Page 45 of 96... -
Page 46: Sst 39Vf64Xxb Application Flash Command Cycles
= 0xFFFF_FFFF_FFFF_FFFF at the Flash base address for Chip Erase or at the given sector/block address for Sector/Block Erase. Figure 5-19 : SST 39VF64xxB Application Flash Command Cycles TVME8240A User Manual Issue 1.1 Page 46 of 96... -
Page 47: Sst Application Flash Sector Maps
The four SST39VF3201/3202 Flash devices provide a total of 1024 sectors (16 Kbyte each) or 64 blocks (256 Kbyte each). Sector Size Sector Sector Address Range (Byte) 4 x 4 K 0x7000_0000 - 0x7000_3FFF 4 x 4 K 0x7000_4000 - 0x7000_7FFF TVME8240A User Manual Issue 1.1 Page 47 of 96... -
Page 48: Figure 5-22 : Sst39Vf320X Sector Map
0x71FF_0000 - 0x71FF_3FFF SA2045 4 x 4 K 0x71FF_4000 - 0x71FF_7FFF SA2046 4 x 4 K 0x71FF_8000 - 0x71FF_BFFF SA2047 4 x 4 K 0x71FF_C000 - 0x71FF_FFFF Figure 5-24 : SST39VF640xB Sector Map TVME8240A User Manual Issue 1.1 Page 48 of 96... -
Page 49: Figure 5-25 : Sst39Vf640Xb Block Map
0x71F0_0000 - 0x71F3_FFFF BA125 4 x 64 K 0x71F4_0000 - 0x71F7_FFFF BA126 4 x 64 K 0x71F8_0000 - 0x71FB_FFFF BA127 4 x 64 K 0x71FC_0000 - 0x71FF_FFFF Figure 5-25 : SST39VF640xB Block Map TVME8240A User Manual Issue 1.1 Page 49 of 96... -
Page 50: Spansion 29Gl0Xxa Flash Types
Bottom Boot Sectors (4 x 8 Kbyte each) Note: The 64 bit Application Flash Bank is build by using four parallel x16 Flash devices. Figure 5-26 : Supported Spansion Application Flash Types TVME8240A User Manual Issue 1.1 Page 50 of 96... -
Page 51: Spansion Application Flash Command Cycles
WBL = Additional Write Buffer Location (Address must be within same Write Buffer Page as PA. Each Write- Buffer-Page has a 32 byte address boundary). Figure 5-27 : Spansion Application Flash Command Cycles TVME8240A User Manual Issue 1.1 Page 51 of 96... -
Page 52: Spansion Application Flash Identifier
5.2.2.4 Spansion Application Flash Write Buffer Programming The Spansion S29GL0xxA Flash devices in x16-Mode may use Write-Buffer programming or direct programming. For Write-Buffer Programming please see the write buffer programming description in the Spansion Boot Flash section. TVME8240A User Manual Issue 1.1 Page 52 of 96... -
Page 53: Spansion Application Flash Flowcharts
0x707E_0000 - 0x707E_BFFF SA36 4 x 8K 0x707E_C000 - 0x707E_FFFF SA37 4 x 8K 0x707F_0000 - 0x707F_BFFF SA38 4 x 8K 0x707F_C000 - 0x707F_FFFF Figure 5-30 : S29GL016A-R1 Application Flash Sector Map TVME8240A User Manual Issue 1.1 Page 53 of 96... -
Page 54: Figure 5-31 : S29Gl016A-R2 Application Flash Sector Map
0x70FC_0000 - 0x70FC_BFFF SA63 4 x 8K 0x70FC_C000 - 0x70FC_FFFF SA64 4 x 8K 0x70FD_0000 - 0x70FD_BFFF SA65 4 x 8K 0x70FD_C000 - 0x70FD_FFFF SA66 4 x 8K 0x70FE_0000 - 0x70FE_BFFF TVME8240A User Manual Issue 1.1 Page 54 of 96... -
Page 55: Figure 5-32 : S29Gl032A-R3 Application Flash Sector Map
0x7008_0000 - 0x700B_FFFF 4 x 64K 0x700C_0000 - 0x700F_FFFF … … … SA60 4 x 64K 0x70F0_0000 - 0x70F3_FFFF SA61 4 x 64K 0x70F4_0000 - 0x70F7_FFFF SA126 4 x 64K 0x70F8_0000 - 0x70FB_FFFF TVME8240A User Manual Issue 1.1 Page 55 of 96... -
Page 56: Figure 5-34 : S29Gl064A-R3 Application Flash Sector Map
0x71F0_0000 - 0x71F3_FFFF SA132 4 x 64K 0x71F4_0000 - 0x71F7_FFFF SA133 4 x 64K 0x71F8_0000 - 0x71FB_FFFF SA134 4 x 64K 0x71FC_0000 - 0x71FF_FFFF Figure 5-35 : S29GL064A-R4 Application Flash Sector Map TVME8240A User Manual Issue 1.1 Page 56 of 96... -
Page 57: Vme Bus Interface
The Tundra Universe-II VME/PCI bridge is used as the TVME8240A VME PCI bridge. The Universe-II is accessible on both the VME bus and the TVME8240A PCI bus. Please refer to the Universe-II manual for a detailed description of the Universe-II VME/PCI bridge. -
Page 58: Universe-Ii Reset Signals
Universe-II VR_BERR (VME BERR#) input while the TVME8240A is the VME Bus Master. The TVME8240A VME bus error interrupt is handled via the Utility Registers in the Peripheral Devices address space. Please see the Address Map section for details. -
Page 59: Ethernet Interface
7 Ethernet Interface The TVME8240A V2.0 provides two Intel 82551 Fast Ethernet Controllers. There is one 10Base- T/100Base-TX interface available on a RJ45 connector at the front panel and a second 10Base- T/100Base-TX interface available on the VME P2 connector for back-I/O. -
Page 60: 82551 Configuration Eeprom
Figure 7-2 : Intel 82551 Configuration EEPROM Settings 7.3 Media Capabilities • IEEE 802.3 10Base-T / 100Base-TX interface, available at a RJ45 front panel connector • IEEE 802.3 10Base-T / 100Base-TX interface, available at the VME P2 connector TVME8240A User Manual Issue 1.1 Page 60 of 96... -
Page 61: Scsi Bus Interface
The TVME8240A-12/-22 provides the LSI 53C875 SCSI Controller for the TVME8240A-12/-22 SCSI bus interface. The 53C875 is accessible on the TVME8240A-12/-22 PCI bus (PCI device no. 15). The 53C875 INT# interrupt output is mapped to the serial interrupt no. 3 of the MPC8245 PIC. -
Page 62: 53C875 Pin Usage
8 bit SCSI interface, any 16 bit SCSI communication will fail. If there is any 16 bit SCSI target device on the TVME8240A-12/-22 VME P2 8 bit SCSI interface, the 53C875 (TVME8240A-12/-22 SCSI controller) must be configured for using 8 bit SCSI communication only, by software (clearing the Enable Wide SCSI bit in the 53C875 SCNTL3 register) during the 53C875 configuration process. -
Page 63: Ip Bus Interface
A Xilinx FPGA is used on the PCI9030 local bus to implement the IP interface control and register functions. 9.1 PCI9030 PCI Target Chip The PCI9030 provides four local spaces 0:3 that are used by the TVME8240A IP interface. Basic PCI9030 register configuration is loaded from a serial EEPROM after power-up or board reset. -
Page 64: Pci9030 Pci Header
HS CSR HS NxtCap HS CapID 0x0000_4C06 0x4C VPD Address VPD NxtCap VPD CapID 0x0000_0003 0x50 VPD Data 0x0000_0000 Read back Value after writing all 1's. Figure 9-1 : PCI9030 PCI Header TVME8240A User Manual Issue 1.1 Page 64 of 96... -
Page 65: Local Configuration Register
Serial EEPROM / Interrupt Control & Status PROT_AREA / 0x0030_0049 INTCSR 0x50 Miscellaneous CNTRL 0x007A_4000 0x54 General Purpose I/O GPIOC 0x0224_9252 Figure 9-2 : PCI9030 Local Configuration Register Shown values are register values after serial EEPROM configuration. TVME8240A User Manual Issue 1.1 Page 65 of 96... -
Page 66: Pci9030 Configuration Eeprom
0x0000 0x3C Local 0x16 MSW Local Space 0 Remap LAS0BA[31:16] 0x0800 0x3E Local 0x14 LSW Local Space 0 Remap LAS0BA[15:0] 0x0001 0x40 Local 0x1A MSW Local Space 1 Remap LAS1BA[31:16] 0x0400 TVME8240A User Manual Issue 1.1 Page 66 of 96... -
Page 67: Figure 9-3 : Pci9030 Configuration Eeprom Settings
LSW Power Management Data Select 0x0000 0x84 Local 0x76 MSW Power Management Data Scale 0x0000 0x86 Local 0x74 LSW Power Management Data Scale 0x0000 Figure 9-3 : PCI9030 Configuration EEPROM Settings TVME8240A User Manual Issue 1.1 Page 67 of 96... -
Page 68: Ip Interface
The IP FPGA also provides the IP Interface Control Registers. The IP FPGA is configured at power-up or board reset by an on board serial Flash. Board Initialization software should verify successful FPGA configuration in the Utility Status Register. TVME8240A User Manual Issue 1.1 Page 68 of 96... -
Page 69: Pci9030 Local Space Assignment
IP B CONTROL 0x06 IP C CONTROL 0x08 IP D CONTROL 0x0A RESET 0x0C STATUS 0x0E Reserved 0x10 - 0xFF Reserved Figure 9-6 : Local Space 0 Address Map (IP Interface Register) TVME8240A User Manual Issue 1.1 Page 69 of 96... -
Page 70: Ip Interface Register
The Revision ID Register shows the revision of the on board IP FPGA logic. Name Description (MSB) Read : Undefined Write : No Effect Read: FPGA Logic Revision ID REV_ID Write : No Effect (LSB) Figure 9-7 : Revision ID Register TVME8240A User Manual Issue 1.1 Page 70 of 96... -
Page 71: Ip X Control Registers
If IP recover time is enabled for an IP slot, an IP cycle for this slot will not begin until the IP recover time is expired. The IP recover time is app. 1µs. TVME8240A User Manual Issue 1.1 Page 71 of 96... -
Page 72: Reset Register
Write : (LSB) 0 : No Effect 1 : Assert IP RESET# Signal (Automatic Negation) Figure 9-9 : Reset Register The IP RESET# signal is also asserted at power-up or board reset. TVME8240A User Manual Issue 1.1 Page 72 of 96... -
Page 73: Status Register
0 : No Error on IP_C ERR_C 1 : IP_C ERROR# Signal Asserted Write : No Effect Read : 0 : No Error on IP_B ERR_B 1 : IP_B ERROR# Signal Asserted Write : No Effect TVME8240A User Manual Issue 1.1 Page 73 of 96... - Page 74 0 : No Interrupt 1 Request on IP_A 1 : Active IP_A Interrupt 1 Request INT1_A Write : 0 : No Effect 1 : Clear Edge Sensitive IP_A Interrupt 1 Status TVME8240A User Manual Issue 1.1 Page 74 of 96...
-
Page 75: Local Space 1 Address Map
Figure 9-11 : Local Space 1 Address Map (IP A-D ID, INT, I/O Space) The TVME8240A will perform write cycles to the IP ID space. Any access to the IP INT space will assert the IP INTSEL# signal on the selected IP slot. The TVME8240A will perform write cycles to the IP INT space. -
Page 76: Local Space 3 Address Map
Upon detecting PIC Serial Interrupt No. 4 read the IP Status Register to determine the IP interrupt source. Timeout interrupts and edge sensitive IP interrupts must be cleared in the IP Status Register. Error interrupts should be disabled after being noticed once. TVME8240A User Manual Issue 1.1 Page 76 of 96... -
Page 77: Pci Device Summary
10 PCI Device Summary Figure 10-1 : PCI Device Summary TVME8240A User Manual Issue 1.1 Page 77 of 96... -
Page 78: Board I/O
Abort Switch LAN 1 IP Slot C VME P2 SCSI (SCSI, COM, LAN 2, IP Slot D REMOTE) REMOTE XILINX MPC8245 PCI Expansion Connector JTAG COP/JTAG Figure 11-1 : Board I/O Overview TVME8240A User Manual Issue 1.1 Page 78 of 96... -
Page 79: Jumper
The TVME8240A-12/-22 always terminates the following wide SCSI bus signals: SCSI_PAR1, SCSI_D[15:8]#. If the TVME8240A-12/-22 is part of a wide SCSI bus segment, it must reside at one end of the wide SCSI bus segment. TVME8240A User Manual Issue 1.1... -
Page 80: Boot Select Jumper
Figure 11-5 : VME System Controller Jumper The VME system controller jumper sets the Universe-II BGIN3# input signal, which the Universe-II samples at the end of VME SYSRST# to determine the VME System Controller mode. TVME8240A User Manual Issue 1.1 Page 80 of 96... -
Page 81: Header
11.3 Header 11.3.1 Remote Front Header The Remote Front Header could be used to control the TVME8240A front panel switches from a remote location and to indicate the TVME8240A front panel LED status at a remote location. Signal Signal ACTIVITY_LED#... -
Page 82: Failure Led
• IP Slot C/D +5V • IP Slot A/B/C/D +12V • IP Slot A/B/C/D -12V • SCSI Term +5V (TVME8240A-12/-22 only) 11.4.3 Activity LED The Activity LED (ACT) (green) is set by hardware control if there is any activity on the Local Memory bus or PCI bus. -
Page 83: Switches
A board reset will perform a general board hardware reset, re-configuration and reset of the IP FPGA, PCI reset and CPU reset. If the TVME8240A is the VME bus system controller, a board reset will also assert a VME bus system reset. -
Page 84: Connectors
VME_AM4 VME_A15 VME_A7 VME_IRQ7# VME_A14 VME_A6 VME_IRQ6# VME_A13 VME_A5 VME_IRQ5# VME_A12 VME_A4 VME_IRQ4# VME_A11 VME_A3 VME_IRQ3# VME_A10 VME_A2 VME_IRQ2# VME_A9 VME_A1 VME_IRQ1# VME_A8 -12V +12V Figure 11-9 : VME P1 Connector TVME8240A User Manual Issue 1.1 Page 84 of 96... -
Page 85: Vme P2 Connector
For each serial port, only one connection scheme is allowed at a time, either via the VME P2 connector or via the front plate DB9 connector. Please see the SCSI Interface section for using 16 bit SCSI Targets on the VME P2 connector. TVME8240A User Manual Issue 1.1 Page 85 of 96... -
Page 86: Ip Interface Connectors
The following signals have an on board pull-up resistor (4K7, 5V): ACK#, INTREQ0#, INTREQ1#, ERROR#, STROBE#, RSV0, RSV1, DMAREQ0#, DMAREQ1#, DMAACK#, DMAEND#. DMA is not supported on the TVME8240A IP interface. TVME8240A User Manual Issue 1.1 Page 86 of 96... -
Page 87: Ip P2 Connector
+12V -12V PERR# SERR# LOCK# SDONE DEVSEL# SBO# TRDY# IRDY# STOP# FRAME# ACK64# REQ64# RST# C/BE1# C/BE0# C/BE3# C/BE2# AD11 AD10 AD13 AD12 AD15 AD14 AD17 AD16 AD19 AD18 AD21 AD20 TVME8240A User Manual Issue 1.1 Page 87 of 96... -
Page 88: Figure 11-12 : Pci Expansion Connector
Signal Signal AD23 AD22 AD25 AD24 AD27 AD26 AD29 AD28 AD31 AD30 Figure 11-12 : PCI Expansion Connector The PCI Expansion Connector type used is AMP/TYCO 2-767004-4. TVME8240A User Manual Issue 1.1 Page 88 of 96... -
Page 89: Scsi Interface Connector
SCSI_D6# SCSI_D7# SCSI_PAR0 TERMPWR TERMPWR SCSI_ATN# SCSI_BSY# SCSI_ACK# SCSI_RST# SCSI_MSG# SCSI_SEL# SCSI_CD# SCSI_REQ# SCSI_IO# SCSI_D8# SCSI_D9# SCSI_D10# SCSI_D11# Figure 11-13 : SCSI Connector The SCSI connector type used is AMP/TYCO 787082-7. TVME8240A User Manual Issue 1.1 Page 89 of 96... -
Page 90: Serial Interface Connectors
DB9 connector at the front plate. The DB9 connector type used is AMP/TYCO 747840-4. Serial port 1 mode is always RS232. Serial port 2 mode is programmable for RS232 (default) or RS422 mode. TVME8240A User Manual Issue 1.1 Page 90 of 96... -
Page 91: Lan Rj45 Connector
11.6.6 LAN RJ45 Connector Signal Figure 11-16 : LAN RJ45 Connector The LAN RJ45 connector type used is HALO HFJ-2450E-L11. TVME8240A User Manual Issue 1.1 Page 91 of 96... -
Page 92: Installation And Use Notes
12 Installation and Use Notes 12.1 NVRAM Real-Time Clock Control The TVME8240A provides a M48T37 NVRAM / RTC device with a snaphat battery plugged on top. The snaphat battery provides power for the SRAM cells when the main power supply is off. -
Page 93: Technical Information
• Four cascadable 31 bit timer 13.2 Memory • 64 Mbyte (TVME8240A-1x) or 256 Mbyte (TVME8240A-2x) 64 bit wide SDRAM (100 MHz) • 8 Mbyte (TVME8240A-1x) or 32 Mbyte (TVME8240A-2x) 64 bit wide Flash Memory • 32 Kbyte NVRAM (M48T37) with exchangeable battery •... -
Page 94: Asynchronous Serial Interface
• 8 Mbyte MEM space (8/16 bit) • 4 Mbyte MEM space (8 bit linear) 13.8.2 I/O Interface • Four 50-pin planar connectors for ribbon cable front-I/O • 1A max continuous dc current per IP I/O line TVME8240A User Manual Issue 1.1 Page 94 of 96... -
Page 95: Power Requirements
13.9 Power Requirements The TVME8240A uses the +5V, +12V and -12V power supply from the VME P1 and P2 connectors as the main power supply. + 5V Supply: On board load: 4A (max), (2A typ) Additional load by optional I/O: •... -
Page 96: Physical Data
5% to 90% (non-condensing) 13.10.5 Form Factor • Standard one slot 6U VME • 3-row (a, b, c) VME P1 & P2 connectors (optional PCI expansion board occupies an additional VME slot if installed) TVME8240A User Manual Issue 1.1 Page 96 of 96...
Need help?
Do you have a question about the TVME8240A and is the answer not in the manual?
Questions and answers