Sony CDL1100 Service Manual page 27

Pin No. Pin Name
51
VSS
52 VDD
53
XRES
54 MA0
55
MA1
56 MA2
57
MA3
58 MA4
59
MA5
60
MA6
61 VSS
62
MA7
63 MA8
64
MA9
65 XRAS
66
XUCAS
67 XLCAS
68
XMWR
69
VSS
70 VDD
71
MDB0
72 MDB1
73
MDB2
74 MDB3
75
MDB4
76
MDB5
77
MDB6
78
MDB7
79 VSS
80
MDB8
81 MDB9
82
MDBA
83 MDBB
84
MDBC
85
MDBD
86
MDBE
87
MDBF
88 VSS
89
VDD
90 EXCK
91
SBIN
92 SBSY
93
WFCK
94
C2P0
95
BCLK
96
DATA
97
LRCK
98
VSS
99 DSPCK
100
GSCR
I/O
– Ground
– Power supply (+5V)
I CXD1804R reset signal
O Address bus output bit0 to buffer memory
O Address bus output bit1 to buffer memory
O Address bus output bit2 to buffer memory
O Address bus output bit3 to buffer memory
O Address bus output bit4 to buffer memory
O Address bus output bit5 to buffer memory
O Address bus output bit6 to buffer memory
– Ground
O Address bus output bit7 to buffer memory
O Address bus output bit8 to buffer memory
O Address bus output bit9 to buffer memory
O Buffer memory RAS (Row Address Strobe) signal
O Buffer memory CAS (Column Address Strobe) signal
O Buffer memory CAS (Column Address Strobe) signal
O Buffer memory data write strobe signal
– Ground
– Power supply (+5V)
I/O Buffer memory data bus bit0
I/O Buffer memory data bus bit1
I/O Buffer memory data bus bit2
I/O Buffer memory data bus bit3
I/O Buffer memory data bus bit4
I/O Buffer memory data bus bit5
I/O Buffer memory data bus bit6
I/O Buffer memory data bus bit7
– Ground
I/O Buffer memory data bus bit8
I/O Buffer memory data bus bit9
I/O Buffer memory data bus bit10
I/O Buffer memory data bus bit11
I/O Buffer memory data bus bit12
I/O Buffer memory data bus bit13
I/O Buffer memory data bus bit14
I/O Buffer memory data bus bit15
Ground
–
– Power supply (+5V)
O SBIN reading clock (Connected to CXD3000 EXCK pin/pin 65)
I Subcode serial signal (Connected to CXD3000 SBSO pin/pin 64)
I Subcode sync signal (Connected to CXD3000 SBSY pin/pin 63)
I Write frame clock (Connected to CXD3000 WFCK pin/pin 62)
I C2 pointer signal, indicating an error in MDAT.
I Bit clock, MDAT strobe signal
I Serial data stream from DSP for CD
LR signal, indicating Lch and Rch of MDAT.
I
– Ground
Enter DSP clock
I
I SCOR syncronizing with DSP data output (Connected to CXD3000 GRSCOR pin/pin 113)
Function
27