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Schematic Diagram - Sanyo MCD-ZX600F Service Manual

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IC BLOCK DIAGRAM & DESCRIPTION
IC701 LC587008(4 bit Micro processor)
Function
Option
Pin No.
V
24
DD
Power supply
V
23
SS
LCD drive power supply
NON
1/1 bias
1/2 bias
1/3 bias
V
1
22
DD
VDD
V
2
21
DD
VDD1
VDD2
VSS
Switching pin used to supply the LCD drive voltage to the VDD1 and
V
2 PINS
DD
CUP1
3
Connect a nonpolarized capacitor between CUP1 and CUP2 when
CUP2
4
1/2 or 1/3 bias is used
Leave open when a bias other than 1/2 or 1/3 is used.
System clock oscillator connections
CF specifications
CFIN
Input
25
Ceramic resonator connection (CF specifications)
RC specifications
RC component connection (RC specifications)
External
External signal input pin (CFOUT is left open)
Specifications
26
This oscillator is stopped by the execution of aSTOP or SLOW
CFOUT
Output
Not used
instruction.
Referenc e calculation(cl ock specification s,LCD alternain g frequency),
XTIN
Input
20
32k specifications
system clock oscillator
65k specifications
32 kHz crystal resonator connection
38k specifications
65 kHz crystal resonator connection
Output
19
Not used
XTOUT
This oscillator is stopped by the execution of aSTOP instruction.
The pull-up or pull-
Input-only ports
Transistor to hold
down resistor are
S1
27
Input pins used to read data into RAM
a low or high level
on.
S2
28
Built-in 7.8 ms and 1.95 ms chatter rejection circuits
Input
Selection of either
Note:
S3
29
Built-in pull-up/pull-down resistors
pull-up or pull-
Note: The 7.8 ms and 1.95 ms times are the times when f 0 is
S4
30
down resistor
32.768kHz.
The pull-up or pull-
down resistors are
I/O ports
on.
Transistors to hold
Input pins used to output read data into RAM
K1
31
Note:
a low or high level
Output pins used to output data from RAM
K2
32
I/O
Built-in 7.8 ms and 1.95 ms input-mode chatter rejection circuits.
Selection of either
33
K3
pull-up or pull-
The selection of 7.8 or 1.95 ms is linked to that for the S ports.
34
K4
down resistor
Note: The 7.8 ms and 1.95 ms times are the times when f 0 is
Input mode
32.768 kHz.
Outpu t latch data is
set high.
I/O ports
M1
35
Input pins used to read data into RAM
M2
36
Output pins used to output data from RAM
The same as K1 to
The same as K1 to
I/O
M3
37
M4 is used as the external clock input pin in Tm2 mode 3.
K4
K4
*The minimum period for the external clock is twice the cycle time.
M4
38
Built-in pull-up/pull-down resistors
A1
11
I/O ports
A2
12
Input pins used to read data into RAM
The same as K1 to
The same as K1 to
I/O
A3
13
Output pins used to output data from RAM
K4
K4
Built-in pull-up/pull-down resistors
A4
14
P1
15
I/O ports
P2
16
The same as K1 to
The same as K1 to
I/O
17
Function: The same as pins A1 to A4
P3
K4
K4
P4
18
Continued from preceding page.
QIP-80
At reset
Pin
I/O
Function
Pin No.
I/O ports
Tra nsis tors to hold
Function: The same as for pins A1 to A4
a low or high leve l
Sel ecti on of eith er
Pins So1 to So3 area also used for the serial interface.
pull -up or pull-
So1
7
Use of these pins inserial mode can be selected under program
dow n resis tors
So2
8
cotrol.
I/O
Inte rna l seria l clock
So3
9
Pin functions: SO1:Serial input pin
divi sor selecti on
So4
10
SO2:Serial output pin
SO3:Serial clock pin
I
The serial clock pin can be switched between internal and external,
II
and between rising edge output and falling edge output.
III
Pins N1 to N4
Output-only ports
outpu t circuit type:
Output pins used to output data from RAM
N1
39
An alarm signal can be output from pin N4.(Note that this is only
N2
40
when the N4 output latch is low.)
Output
N3
41
An alarm signal modulated at 1,2 or 4 kHz can be output.(These
N4
42
Pins N1 to N4
frequencies are output when f 0 is 32.768 kHz.)
output level
A carrier signal can be output from N3.(Note that this is only
when the N3 output latch is low.)
Tran sistors to hold
a low or high level
Input ports
Select ion of either
External interrupt request inputs
pull-up or pull-
INT
Input
6
Input pins used to read data into RAM
down resist ors
Input detection can be performed on either rising or falling edges.
Signal convers ion
Built-in pull-up/pull-down resistors
(rising/f alling)
selectio n
LSI internal reset input
*Onl y when the
The reset input level can be selected to be either high or low.
inpu t resisto r open
RES
Input
5
Built-in pull-up/pull-down resistors
spec ificat ion is
selec ted
Note: The reset pulse must be at least 500us.
These pins go
Test input
to the floatin g
TST
Input
43
QIP80 products: Connect to Vss.
sta te when
Chip products : Leave open or connect to Vss.
res et is cleare d.
LCD driver/
general-purpose
output switching
LCD panel drive/general-purpose output
LCD drive type
The se pins go
switching
LCD panel drive
to the floatin g
STATIC
sta te when
1/2 bias-1/2 duty
res et is cleare d.
1/2 bias-1/3 duty
1/2 bias-1/4 duty
1/3 bias-1/3 duty
1/3 bias-1/4 duty
Types I to V can be specified as mask options.
Seg1,
44,
General-purpose output mode
Seg2 to
Output
45 to
CMOS
Seg35
78
P-channel open drain
N-channel open drain
Types I to III can be specified as mask options.
General-purpose
output circuit
LCD/g eneral -purpo se output contro l is handle d by the segme nt PLA,
switching
and thus program control is not required.
These pins support output latch control on reset and in standby
states when the oscillators are stopped.
Arbit rary combinat ions of LCD drive and gene ral-p urpos e output s can
be used.
Outpu t latc h con trol
in standb y mode s
LCD panel drive common polarity outputs
The table below shows how these pins are used depen ding on the duty
used.( values for alterna ting freque ncy reflect a typical specif ication of
32.768 MHz for f 0.)
Static duty
1/2 duty
1/3 duty
1/4 duty
COM1
2
COM2
1
COM1
Output
COM3
80
COM2
COM4
79
COM3
COM4
Alternation
32 Hz
32 Hz
32 Hz
42.7 Hz
32 Hz
frequency
Note: A cross( X ) indicates that the pin is not used with that duty type.
- 10 -
SCHEMATIC DIAGRAM (RADIO)
Option
At reset
The same as for K1
to K4
1/1
1/2
1/4
The outp ut level s on
pins N1 to N4 can be
spec ified as an opti on
LCD drive
All segment s on
All segments off
*:Determined by
mask options
STATIC
General purpose
1/2 bias-1/2
outputs
duty
High level
1/2 bias-1/3
Low level
duty
Determined by
1/2 bias-1/4
mask options
duty
Note:When a
1/3 bias-1/3
comb inatio n of
duty
LCD drive and
1/3 bias-1/4
gene ral-
duty
purpo se
outpu ts,the
outpu t state is
eithe r:
CMOS
All lit/hig h level
P-channel
All off/low level.
open drain
These pins go to
N-channel
the static drive
open drain
mode during the
reset period.
The static drive
waveform is output
during the reset
period.
*There are cases
where the
alternati ng
frequenc y stops for
the CF,RC and
external clock
specifica tions.
(These cases differ
dependi ng on option
specifica tions.)
This is a basic schematic diagram.
- 11 -

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