Block Diagram (7) - Sony FD Trinitron KV-28DS65U Service Manual

5-1. BLOCK DIAGRAMS (7)
TO N BOARD
CN3302
14
15
18
17
19 PP7/PST3
7 PP6/PST2
20 PP5/PST1
8 PP4/PST0
21 PP3/DDATA3
9 PP2/DDATA2
22 PP1/DDATA1
10 PP0/DDATA0
OPEN
4 RESET
IRQ1/IPL2 62
C53
46
WEI
40 A26/CS6/WEI
CS2
(1/3) 45 CS2
61
ATA
RXD2
136
RXD2
TXD2
137 TXD2
IRQ4/IPL1 63
127 TMS/BKPT
64
IRQ1/IPL0
121
TRST/DSCLK
DMXTRQ1
TO N
124
TD0/DS0 BOARD
R/W
(1/2)
126
TD1/DS1
PP7/PST3 38
A25/CSS
151 PP7/PST3
PP6/PST2 54
R/W
152 PP6/PST2
PP5/PST1
153
PP5/PST1
PP4/PST0
154
PP4/PST0
PP(0) - PP(7)
PP3/DDATA3
156 PP3/DDATA3
PP2/DDATA2
157
PP2/DDATA3
PP1/DDATA1 41
158 WE/A17/LS7
PP1/DDATA3
PP0/DDATA0
159 PP0/DDATA0
59
RSTI
DO 120
.
IC3308
1 A(0) 119
CPU .
.
2 117
~
.
4 113
. ~
5 111
. .
7 109
. ~
8 107
. .
105
10
. ~
103
11
. .
101
13
. ~
99
14
. .
97
16
. ~
TO N BOARD A(0)-A(23)
D(0)-D(31)
95
17
(1/3)
. .
93
19
. ~
91
20
. .
89
22
. ~
87
23
.
85
25
. ~
83
26
. .
28 81
. ~
29 D31 79
.
31
DRAMW
.
78
DRAMW
32
.
CAS3
34 76
CAS3
.
35 A(23)
CAS2
75
CAS2
CAS1
CAS1 74
CAS0
CAS0 72
RAS0
71
RASO
CTSI 138
RTSI 139
141
RXDI
142
TXDI
45
IC3312
3 INPUTS AND GATES
12 1Y
DEMUXACK
1 2B 4
1A
TO N BOARD
TO N BOARD
DMXTRQO AVDTACK
13 5
1C 2C
(1/2)
10 9
3B 3A
6 2Y
IC3320
NAND GATES
5
2B
6
2Y
1Y 3
1A 1
TO N BOARD
13 AVIRQ
4A 2
1B
(1/2)
IC3318
SELECTORS
TO N BOARD
ADVS
13 7
4L1 2Y
(1/2)
1 9
5 3Y
1Y 4
5
2L0
+5V
IC3301
1 2
RESET
IC3315 IC3316
GP OUT BY LATCH GP INPUT BY LATCH
D (24)
D (24)
3 2
1D 1Q
D (25)
D (25)
1 4 1 5
2D 2Q
D (26) D (26)
7 C 11 11 C 6
3D 3Q
D (27) D (27)
8 8Q 19 18 8D 9
4D 4Q
D (28) D (28)
13 6 12
5D 3Q 5Q
D (29) D (29)
14 15
6D 4Q 9 6Q
D (30) D (30)
17 16
7D 7Q
D (31) D (31)
18 8D 8Q 19
TO N BOARD
(1/3)
IC3317
19 2G 1A1 2
11 2A1 2Y4 3
+5V
18 1Y1 1A2 4
8 6
7
5 3
4
17 2A4 2Y2 7
2 1
12 1Y4 1A4 8
CN3301
MODEM
13 9
2A2 2Y1
OUT
N (
(2/2)
DIGITAL
PROCESSING
(1/2)
IC3313
NAND GATES
13
4B
10
3B
9 3A
ACTAVRST TO N BOARD
TO N BOARD R/W 12
4A
3 1Y
(1/2)
(2/2)
1 1A
2
1B
IC3310
8 MBIT FLASH
12 RESET D16 45
.
IC3307
43
16 MBIT ED DRAM UPPER
.
41
.
39 A0
21
. ~
DQ16 49
36
23
~
. .
11
/WE 46
34
28
.
. ~
44
32
25 A1 32
~
~ . .
41
30 D(16)-D(24)
18 D(16)-D(31) 24
.
. . .
10
44
8 27 A9
~
~ .
A(1)-A(19)
7
42
1
DRAMW .
. . 17
/WE
5
40
48
~
.
. CAS1
2
38 35 /LCAS DQ1
17
.
.
35 CAS0
16 A19
34 /UCAS
.
33
RAS0
. 18 /RAS
31
.
D31 29
R/W 28
IC3309
8 MBIT FLASH
12 RESET D16 29
.
IC3304
31
11 /WE
16 MBIT ED DRAM UPPER
.
33
.
35 A0
21
. ~
DQ16
38 49
23
A1 ~
25 . .
~ 40 46
28
.
18 . ~
. 42 44
32
~
8 .
.
~ 44 41 D(0)-D(15)
A(1)-A(19) D(16)-D(31) 24
.
1 .
.
. 30 10
27 A9
~
48 .
. 32 7
DRAMW .
17 .
17 /WE
. 34 5
~
16 A19 .
CAS1
36 35 /LCAS DQ1 2
.
CAS0
39
34 /UCAS
.
41
RAS0
. 18
/RAS
43
.
D31 45
R/W 28
A(9)-A(15), A(17), A(19), A(21)
46
)