MSI MS-7510 User Manual page 61

M S-7510 M ainboard
M emory Timings
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to [Auto By SPD] enables DRAM timings
and the following related items to be determined by BIOS based on the configu-
rations on the SPD. Selecting [Manual] allows users to configure the DRAM
timings and the following related items manually.
CAS Latency (CL)
W hen the Memory Timings sets to [Manual], the field is adjustable.This con-
trols the CAS latency, which determines the timing delay (in clock cycles) before
SDRAM starts a read command after receiving it.
tRCD
W hen the M emory Timings sets to [Manual], the field is adjustable. W hen
DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance.
tRP
W hen the Memory Timings sets to [Manual], the field is adjustable. This item
controls the number of cycles for Row Address Strobe (RAS) to be allowed to
precharge. If insufficient time is allowed for the RAS to accumulate its charge
before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain
data. This item applies only when synchronous DRAM is installed in the system.
tRAS
W hen the Memory Timings sets to [Manual], the field is adjustable. This set-
ting determines the time RAS takes to read from and write to a memory cell.
tRRD
W hen the Memory Timings sets to [Manual], the field is adjustable. Specifies
the active-to-active delay of different banks.
tRC
W hen the Memory Timings sets to [Manual], the field is adjustable. The row
cycle time determines the minimum number of clock cycles a memory row takes
to complete a full cycle, from row activation up to the precharging of the active
r ow.
tWR
W hen the Memory Timings is set to [Manual], the field is adjustable. It speci-
fies the amount of delay (in clock cycles) that must elapse after the completion
of a valid write operation, before an active bank can be precharged. This delay
is required to guarantee that data in the write buffers can be written to the
memory cells before precharge occurs.
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