Sharp QT-CD210H(BL) Serivce Manual page 23

IC802 VHiTC9457F0-1: Servo/Signal Control (TC9457F0) (2/4)
Pin No. Port Name
30 (S12)P4-1 PUSEL2
31* (SO/S11/ NC
SDA)P4-2
32* (SCK/SCL) NC
P4-3
33 TEST0 TEST0
34 TEST1 TEST1
35 TEST2 TEST2
36 TEST3 TEST3
37 TEST4 TEST4
38 TEST5 TEST5
39* (OT19)/HSO /HSO
40* (OT20)SPCK SPCK
41* (OT21)SPDA SPDA
42* (OT22)COFS COFS
43* DOUT DOUT
44* SBSY SBSY
45* SBOK SBOK
46 VDD VDD1
47 VSS VSS1
48 P2VREF P2VREF
49 PDO PDO
50 TMAX TMAX
51 LPFN LPFN
52 LPFO LPFO
53 PVREF PVREF
54 VCOF VCOF
55 AVSS AVSS
56 SLCO SLCO
57 RFI RFI
58 AVDD AVDD
59 RFCT RFCT
60 RFZI RFZI
61 RFRP RFRP
62 FEI FEI
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Terminal Name Input/Output
Input
Input/Output
Input/Output
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
3-bit CMOS I/O ports.
These ports can be set for input or output bit for bit by a program.
These pins serve dual purposes as input or output pins for the serial
interface circuit (SIO).
The SIO is a 2-wire/3-wire compatible serial interface. 4 or 8 bits of serial
data, beginning with the MSB or LSB, are serially output from the SO/SDA,
pin at each clock edge on the SCK/SCL pin, and the data on S11 or S12
pin is serially input to the device.
The serial clock (SCK/SCL) allows selection between the internal (450/225/
150/75 kHz) and external sources and a selection of the active edge, rise or
fall. Moreover, since the clock and data can be output via Nch open-drain
outputs, variouts, device controls and communication between controllers
can be greatly facilitated.
When an SIO interrupt is enabled, an interrupt is generated at completion
of SIO execution and the program jumps to address 4.
All inputs to SIO contain a Schmitt trigger circuit.
Test mode control input pins.
The test mode is selected when these pins are set high and normal
operation is selected when they are low.
CD control output pins.
• /HSO: Playback speed mode output.
High = normal speed; Low = double speed.
• SPCK: Processor status signal readout clock output (176.4kHz)
• SPDA: Processor status signal output.
• COFS: Correction system frame clock output (7.35kHz)
These pins can be switched for output ports by a program.
Digital output pin.
Subcode block sync output pin. It outputs a high at the S1 position when
subcode sync is detected.
Subcode Q data CRCC determination result output pin. It outputs a high
when CRCC check is found OK.
CD unit's digital block power supply pins.
Normally, apply 5V to VDD.
When not using a CD (CD off), this power supply can be turned off, with
only the controller power supply kept active, so that the contrller alone is
operating. In this case, the CD off bit must be set to 1. When this bit is set
to 1, pins 11 through 18 and pins 39 through 42 all are changed for output
ports if they have been set for CD control signal input/output pins.
PLL block-2 VREF pin.
This pin outputs a phase error between EFM and PLCK signals.
TMAX detection result output pin.
Selected by command bit TMPS.
Longer than preset period: Outputs P2VREF.
Shorter than preset period: Low level (Vss).
Within preset period: High impedance.
Inverted input of low-pass filter amp.
Output of low-pass filter amp.
PLL block VREF pin.
VCO filter pin.
Analog block ground pin.
DAC output pin for data slice level generation.
RF signal input pin.
Analog block power supply pin.
RFRP signal center level input pin.
RFRP zero-cross input pin.
RF ripple signal input pin.
Focus error signal input pin.
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QT-CD210H/W
Function