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STR-LV500
Pin No.
Pin Name
53
PAGE0
54
BOOT
55
BTACT
56
BST
57
MOD1
58
MOD0
59
EXLOCK
60
VDDI
61
VSS
62
A17
63
A16
64 to 66
A15 to A13
67 to 69
GP10 to GP8
70
VDDI
71
VSS
72 to 75
D15/GP7 to D12/GP4
76
VDDE
77 to 80
D11/GP3 to D8/GP8
81
VSS
82 to 85
A9 to A10
86
TDO
87
TMS
88
XTRST
89
TCK
90
TDI
91
VSS
92 to 97
A8 to A3
98,99
D7,D6
100
VDDI
101
VSS
102 to 105
D5 to D2
106
VDDE
107,108
D1,D0
109,110
A2,A1
111
VSS
112
A0
113
PM
114
SD13
115
SD14
116
SYNC
117 to 119
VSS
120
VDDI
10
I/O
O
Not used (open)
I
Not used (connected to ground)
O
Not used (open)
I
Boot strap signal input from MB90478
I
Mode input (connected to VDD)
I
Mode input (connected to ground)
I
Lock signal input to LC89056W
—
Power supply (+2.5V)
—
Ground
O
Not used (open)
O
Not used (open)
O
Address bus output to the SRAM
I/O
External memory data I/O general purpose port terminal GP
—
Power supply (+2.5V)
—
Ground
I/O
SRAM data bus
—
Power supply (+3.3V)
I/O
SRAM data bus
—
Ground
O
Address bus output to the SRAM
O
Not used (open)
I
Not used (open)
I
Not used (open)
I
Not used (open)
I
Not used (open)
—
Ground
O
Address bus output to the SRAM
I/O
SRAM data bus
—
Power supply (+2.5V)
—
Ground
I/O
SRAM data bus
—
Power supply (+3.3V)
I/O
SRAM data bus
O
Address bus output to the SRAM
—
Ground
O
Address bus output to the SRAM
I
PLL initialization input from MB90478
I
Not used (open)
I
Not used (open)
I
Synchronization / asynchronous selection input (pull up)
—
Ground
—
Power supply (+2.5V)
Description
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