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DAQ PCI-MIO E Series User Manual

Multifunction i/o boards for pci bus computers
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PCI-MIO E Series
User Manual
Multifunction I/O Boards for
PCI Bus Computers
January 1997 Edition
Part Number 320945B-01
© Copyright 1995, 1997 National Instruments Corporation. All Rights Reserved.

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  • Page 1 Click here to comment on this document via the National Instruments website at http://www.natinst.com/documentation/daq/ PCI-MIO E Series User Manual Multifunction I/O Boards for PCI Bus Computers January 1997 Edition Part Number 320945B-01 © Copyright 1995, 1997 National Instruments Corporation. All Rights Reserved.
  • Page 2 Mexico 5 520 2635, Netherlands 0348 433466, Norway 32 84 84 00, Singapore 2265886, Spain 91 640 0085, Sweden 08 730 49 70, Switzerland 056 200 51 51, Taiwan 02 377 1200, U.K. 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 Tel: (512) 794-0100...

  • Page 3: Important Information

    The PCI-MIO E Series boards are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

  • Page 5: Table Of Contents

    Chapter 1 Introduction About the PCI-MIO E Series ..................1-1 What You Need to Get Started ..................1-2 Software Programming Choices ...................1-3 National Instruments Application Software ...........1-3 NI-DAQ Driver Software ................1-4 Register-Level Programming .................1-5 Optional Equipment ......................1-6 Custom Cabling ......................1-6 Unpacking ........................1-7...
  • Page 6 (RSE Configuration) ..............4-20 Single-Ended Connections for Grounded Signal Sources (NRSE Configuration) ..............4-20 Common-Mode Signal Rejection Considerations.......... 4-21 Analog Output Signal Connections ................4-22 Digital I/O Signal Connections ..................4-23 PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 7 GPCTR1_UP_DOWN Signal ............4-46 FREQ_OUT Signal ................4-47 Field Wiring Considerations ..................4-48 Chapter 5 Calibration Loading Calibration Constants ..................5-1 Self-Calibration......................5-2 External Calibration ......................5-2 Other Considerations ....................5-3 Appendix A Specifications Appendix B Optional Cable Connector Descriptions © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 8 Analog Output Connections ..............4-23 Figure 4-9. Digital I/O Connections................. 4-24 Figure 4-10. Timing I/O Connections ................ 4-26 Figure 4-11. Typical Posttriggered Acquisition............4-27 Figure 4-12. Typical Pretriggered Acquisition ............4-28 PCI-MIO E Series User Manual viii © National Instruments Corporation...
  • Page 9 Actual Range and Measurement Precision, PCI-MIO-16XE-10 and PCI-MIO-16XE-50 .........3-7 Table 4-1. I/O Signal Summary, PCI-MIO-16E-1 and PCI-MIO-16E-4....4-6 Table 4-2. I/O Signal Summary, PCI-MIO-16XE-10 ..........4-7 Table 4-3. I/O Signal Summary, PCI-MIO-16XE-50 ..........4-9 © National Instruments Corporation PCI-MIO E Series User Manual...

  • Page 11: Organization Of This Manual

    Chapter 4, Signal Connections, describes how to make input and output signal connections to your PCI-MIO E Series board via the board I/O connector. • Chapter 5, Calibration, discusses the calibration procedures for your PCI-MIO E Series board. © National Instruments Corporation PCI-MIO E Series User Manual...

  • Page 12: Conventions Used In This Manual

    PCI-MIO E Series board. • Appendix D, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products. • The Glossary contains an alphabetical list and description of terms used in this manual, including acronyms, abbreviations, definitions metric prefixes, mnemonics, and symbols.
  • Page 13 About This Manual SCXI SCXI stands for Signal Conditioning eXtensions for Instrumentation and is a National Instruments product line designed to perform front-end signal conditioning for National Instruments plug-in DAQ boards. indicates that the text following it applies only to specific PCI-MIO E Series boards.

  • Page 14: Related Documentation

    Customer Communication National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete.

  • Page 15: About The Pci-Mio E Series

    PCI-MIO E Series board. About the PCI-MIO E Series Thank you for buying a National Instruments PCI-MIO E Series board. The PCI-MIO E Series boards are completely Plug and Play, multifunction analog, digital, and timing I/O boards for PCI bus computers.

  • Page 16: What You Need To Get Started

    VirtualBench Your computer 1. Please note that only the PCI-MIO-16XE-50 is currently supported on the Macintosh. Please contact National Instruments for information on Macintosh support for the other boards in the PCI-MIO E Series. PCI-MIO E Series User Manual © National Instruments Corporation...

  • Page 17: Software Programming Choices

    Chapter 1 Introduction Software Programming Choices You have several options to choose from when programming your National Instruments DAQ and SCXI hardware. You can use National Instruments application software, NI-DAQ, or register-level programming. National Instruments Application Software ComponentWorks contains tools for data acquisition and instrument control built on NI-DAQ driver software.

  • Page 18: Ni-Daq Driver Software

    An example of a low-level function is writing directly to registers on the DAQ device. NI-DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak.

  • Page 19: Register-Level Programming

    Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware Register-Level Programming The final option for programming any National Instruments DAQ hardware is to write register-level software. Writing register-level programming software can be very time-consuming and inefficient, and is not recommended for most users.

  • Page 20: Optional Equipment

    Chapter 1 Introduction Optional Equipment National Instruments offers a variety of products to use with your PCI-MIO E Series board, including cables, connector blocks, and other accessories, as follows: • Cables and cable assemblies, shielded and ribbon • Connector blocks, shielded and unshielded 50 and 68-pin screw terminals •...

  • Page 21: Unpacking

    Chapter 1 Introduction Mating connectors and a backshell kit for making custom 68-pin cables are available from National Instruments (part number 776832-01) PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-MIO-16XE-10, and the PCI-MIO-16XE-50 Honda 68-position, solder cup, female connector (part number PCS-E68FS) Honda backshell (part number PCS-E68LKPA)

  • Page 23: Software Installation

    PCI-MIO E Series board and other boards and hardware. The following are general installation instructions, but consult your computer user manual or technical reference manual for specific instructions and warnings. © National Instruments Corporation PCI-MIO E Series User Manual...

  • Page 24: Board Configuration

    Refer to your software documentation for configuration instructions. Board Configuration Due to the National Instruments standard architecture for data acquisition and the PCI bus specification, the PCI-MIO E Series boards are completely software configurable. You must perform two types of configuration on the PCI-MIO E Series boards—bus-related and data...

  • Page 25: Hardware Overview

    RTSI Bus Analog Digital I/O Output Timing/Control Interface Interface Digital I/O (8) Control AO Control DAC0 Data (16) FIFO DAC1 Calibration RTSI Bus DACs Figure 3-1. PCI-MIO-16E-1 and PCI-MIO-16E-4 Block Diagram © National Instruments Corporation PCI-MIO E Series User Manual...

  • Page 26: Figure 3-2. Pci-Mio-16Xe-10 Block Diagram

    Analog Output RTSI Bus Analog Digital I/O (8) Digital I/O Output Timing/Control Interface Interface Control AO Control DAC0 Data (16) FIFO DAC1 Calibration RTSI Bus DACs Figure 3-2. PCI-MIO-16XE-10 Block Diagram PCI-MIO E Series User Manual © National Instruments Corporation...

  • Page 27: Analog Input

    (RSE) input, and differential (DIFF) input. The single-ended input configurations provide up to 16 channels. The DIFF input configuration provides up to eight channels. Input modes are programmed on a per © National Instruments Corporation PCI-MIO E Series User Manual...

  • Page 28: Input Polarity And Input Range

    /2 and + V /2. The PCI-MIO-16E-1 and PCI-MIO-16E-4 have a unipolar input range of 10 V (0 to 10 V) and a bipolar input range of 10 V ( 5 V). PCI-MIO E Series User Manual © National Instruments Corporation...

  • Page 29: Table 3-2. Actual Range And Measurement Precision Pci-Mio-16E-1 And Pci-Mio-16E-4

    The value of 1 LSB of the 12-bit ADC; that is, the voltage increment corresponding to a change of one count in the ADC 12-bit count. Note: See Appendix A, Specifications, for absolute maximum ratings. © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 30 100. These gains are suited for a wide variety of signal levels. With the proper gain setting, you can use the full resolution of the ADC to measure the input signal. PCI-MIO E Series User Manual © National Instruments Corporation...

  • Page 31: Considerations For Selecting Input Ranges

    For example, if you are certain the input signal will not be negative (below 0 V), unipolar input polarity is best. However, if the signal is negative or equal to zero, you will get inaccurate readings if you use unipolar input polarity. © National Instruments Corporation PCI-MIO E Series User Manual...

  • Page 32: Dither

    Dither has the effect of forcing quantization noise to become a zero-mean random variable rather than a deterministic function of the input signal. PCI-MIO E Series User Manual © National Instruments Corporation...

  • Page 33: Multichannel Scanning Considerations

    Refer to Appendix A, Specifications, for a complete listing of settling times for each of the PCI-MIO E Series boards. © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 34 (for example, 100 points from channel 0, then 100 points from channel 1, then 100 points from channel 2, and so on). PCI-MIO E Series User Manual 3-10 © National Instruments Corporation...

  • Page 35: Analog Output

    +10 V onboard reference or an externally supplied reference within 11 V. You do not need to configure both channels for the same range. © National Instruments Corporation 3-11 PCI-MIO E Series User Manual...

  • Page 36: Analog Output Reglitch Selection

    Notice that this reglitch circuit does not eliminate the glitches; it only makes them more uniform in size. Reglitching is normally disabled at startup and your software can independently enable each channel. PCI-MIO E Series User Manual 3-12 © National Instruments Corporation...

  • Page 37: Analog Trigger

    (less than 1 k source impedance) if you plan to enable this input via software. Analog Input PGIA Channels Analog Trigger DAQ-STC Circuit PFI0/TRIG1 Figure 3-5. Analog Trigger Block Diagram © National Instruments Corporation 3-13 PCI-MIO E Series User Manual...

  • Page 38: Figure 3-6. Below-Low-Level Analog Triggering Mode

    LowValue is unused. highValue Trigger Figure 3-7. Above-High-Level Analog Triggering Mode In inside-region analog triggering mode, the trigger is generated when the signal value is between the lowValue and the highValue. PCI-MIO E Series User Manual 3-14 © National Instruments Corporation...

  • Page 39: Figure 3-8. Inside-Region Analog Triggering Mode

    In low-hysteresis analog triggering mode, the trigger is generated when the signal value is less than lowValue, with the hysteresis specified by highValue. highValue lowValue Trigger Figure 3-10. Low-Hysteresis Analog Triggering Mode © National Instruments Corporation 3-15 PCI-MIO E Series User Manual...

  • Page 40: Digital I/O

    DAQ-STC, and these selections are fully software configurable. For example, the signal routing multiplexer for controlling the CONVERT* signal is shown in Figure 3-11. PCI-MIO E Series User Manual 3-16 © National Instruments Corporation...

  • Page 41: Programmable Function Inputs

    PFI pins to output a specific internal timing signal. For example, if you need the UPDATE* signal as an output on the I/O connector, software can turn on the output driver for the PFI5/UPDATE* pin. © National Instruments Corporation 3-17 PCI-MIO E Series User Manual...

  • Page 42: Board And Rtsi Clocks

    RTSI bus. These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals. This signal connection scheme is shown in Figure 3-12. PCI-MIO E Series User Manual 3-18 © National Instruments Corporation...

  • Page 43: Figure 3-12. Rtsi Bus Signal Connection

    Clock switch RTSI_OSC (20 MHz) Figure 3-12. RTSI Bus Signal Connection Refer to the Timing Connections section of Chapter 4 for a description of the signals shown in Figure 3-12. © National Instruments Corporation 3-19 PCI-MIO E Series User Manual...

  • Page 45: Signal Connections

    E Series board and the computer. Maximum input ratings for each signal are given in the Protection column of Tables 4-1, 4-2, and 4-3. National Instruments is liable for any damages resulting from such signal connections. © National Instruments Corporation PCI-MIO E Series User Manual...

  • Page 46: Figure 4-1. I/O Connector Pin Assignment For The Pci-Mio E Series Boards

    PFI4/GPCTR1_GATE PFI5/UPDATE* GPCTR1_OUT PFI6/WFTRIG DGND DGND PFI7/STARTSCAN PFI9/GPCTR0_GATE PFI8/GPCTR0_SOURCE GPCTR0_OUT DGND FREQ_OUT DGND Not available on PCI-MIO-16XE-10 or PCI-MIO-16XE-50 Figure 4-1. I/O Connector Pin Assignment for the PCI-MIO E Series Boards PCI-MIO E Series User Manual © National Instruments Corporation...

  • Page 47: I/O Connector Signal Descriptions

    Scan Clock—This pin pulses once for each A/D conversion in the scanning modes when enabled. The low-to-high edge indicates when the input signal can be removed from the input or switched to another signal. © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 48 As an output, this is the GPCTR1_GATE signal. This signal reflects the actual gate signal connected to the general-purpose counter 1. GPCTR1_OUT DGND Output Counter 1 Output—This output is from the general-purpose counter 1 output. PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 49 Counter 0 Output—This output is from the general-purpose counter 0 output. FREQ_OUT DGND Output Frequency Output—This output is from the frequency generator output. EXTREF is not available on the PCI-MIO-16XE-10 or the PCI-MIO-16XE-50. © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 50 — V cc +0.5 3.5 at (V cc -0.4) 5 at 0.4 50 k pu PFI2/CONVERT* — V cc +0.5 3.5 at (V cc -0.4) 5 at 0.4 50 k pu PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 51 V) (ns) ACH<0..15> 100 G 25/15 — — — 1 nA in parallel with 100 pF AISENSE 100 G 25/15 — — — 1 nA in parallel with 100 pF © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 52 — V cc +0.5 3.5 at (V cc -0.4) 5 at 0.4 50 k pu PFI9/GPCTR0_GATE — V cc +0.5 3.5 at (V cc -0.4) 5 at 0.4 50 k pu PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 53 — DGND — — — — — — Short-circuit — — — to ground DIO<0..7> — V cc +0.5 13 at (V cc -0.4) 24 at 0.4 1.1 50 k pu © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 54 3.5 at (V cc -0.4) 5 at 0.4 50 k pu AI = Analog Input DIO = Digital Input/Output pu = pullup AO = Analog Output DO = Digital Output PCI-MIO E Series User Manual 4-10 © National Instruments Corporation...

  • Page 55: Analog Input Signal Connections

    Warning: Exceeding the differential and common-mode input ranges distorts your input signals. Exceeding the maximum input voltage rating can damage the PCI-MIO E Series board and the computer. National Instruments is liable for any damages resulting from such signal connections. The maximum input voltage ratings are listed in the Protection column of Tables 4-1 to 4-3.

  • Page 56: Figure 4-2. Pci-Mio E Series Pgia

    Nonreferenced or Floating Signal Sources section later in this chapter). If you have a grounded source, you should not reference the signal to AIGND. You can avoid this reference by using DIFF or NRSE input configurations. PCI-MIO E Series User Manual 4-12 © National Instruments Corporation...

  • Page 57: Types Of Signal Sources

    You can configure your PCI-MIO E Series board for one of three input modes—NRSE, RSE, or DIFF. The following sections discuss the use of single-ended and differential measurements and considerations for measuring both floating and ground-referenced signal sources. © National Instruments Corporation 4-13 PCI-MIO E Series User Manual...

  • Page 58: Figure 4-3. Summary Of Analog Input Connections

    Ground-loop losses, V , are added to measured signal Single-Ended — AISENSE AISENSE Nonreferenced (NRSE) AIGND AIGND See text for information on bias resistors. Figure 4-3. Summary of Analog Input Connections PCI-MIO E Series User Manual 4-14 © National Instruments Corporation...

  • Page 59: Differential Connection Considerations (Diff Input Configuration)

    The signal leads travel through noisy environments. Differential signal connections reduce picked up noise and increase common-mode noise rejection. Differential signal connections also allow input signals to float within the common-mode limits of the PGIA. © National Instruments Corporation 4-15 PCI-MIO E Series User Manual...

  • Page 60: Differential Connections For Ground-Referenced Signal Sources

    With this type of connection, the PGIA rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the PCI-MIO E Series board ground, shown as V Figure 4-4. PCI-MIO E Series User Manual 4-16 © National Instruments Corporation...

  • Page 61: Differential Connections For Nonreferenced Or Floating Signal Sources

    AIGND as well as to the negative input of the PGIA, without any resistors at all. This connection works well for DC-coupled sources with low source impedance (less than 100 © National Instruments Corporation 4-17 PCI-MIO E Series User Manual...

  • Page 62: Single-Ended Connection Considerations

    The input signal is tied to the positive input of the PGIA, and the ground is tied to the negative input of the PGIA. When every channel is configured for single-ended input, up to 16 analog input channels are available. PCI-MIO E Series User Manual 4-18 © National Instruments Corporation...
  • Page 63 The coupling is the result of differences in the signal path. Magnetic coupling is proportional to the area between the two signal conductors. Electrical coupling is a function of how much the electric field differs between the two conductors. © National Instruments Corporation 4-19 PCI-MIO E Series User Manual...

  • Page 64: Single-Ended Connections For Floating Signal Sources (Rse Configuration)

    If the input circuitry of a PCI-MIO E Series board were referenced to ground, in this situation as in the RSE input configuration, this difference in ground potentials would appear as an error in the measured voltage. PCI-MIO E Series User Manual 4-20 © National Instruments Corporation...

  • Page 65: Common-Mode Signal Rejection Considerations

    ) must be within 26 V of AIGND. At gains of 10 and 100, this is roughly equivalent to restricting the two input voltages to within 8 V of AIGND. © National Instruments Corporation 4-21 PCI-MIO E Series User Manual...

  • Page 66: Analog Output Signal Connections

    AOGND is the ground reference signal for both analog output channels and the external reference signal. Figure 4-8 shows how to make analog output connections and the external reference input connection to your PCI-MIO E Series board. PCI-MIO E Series User Manual 4-22 © National Instruments Corporation...

  • Page 67: Digital I/O Signal Connections

    Warning: Exceeding the maximum input voltage ratings, which are listed in Tables 4-1, 4-2, and 4-3 can damage the PCI-MIO E Series board and the computer. National Instruments is liable for any damages resulting from such signal connections.

  • Page 68: Figure 4-9. Digital I/O Connections

    TTL signals and sensing external device states such as the state of the switch shown in the figure. Digital output applications include sending TTL signals and driving external devices such as the LED shown in the figure. PCI-MIO E Series User Manual 4-24 © National Instruments Corporation...

  • Page 69: Power Connections

    PCI-MIO E Series board or any other device. Doing so can damage the PCI-MIO E Series board and the computer. National Instruments is liable for damages resulting from such a connection.

  • Page 70: Programmable Function Input Connections

    I/O connector, software can turn on the output driver for the PFI2/CONVERT* pin. Be careful not to drive a PFI signal externally when it is configured as an output. PCI-MIO E Series User Manual 4-26 © National Instruments Corporation...

  • Page 71: Daq Timing Connections

    Figure 4-12 shows a typical pretriggered DAQ sequence. The description for each signal shown in these figures is included later in this chapter. TRIG1 STARTSCAN CONVERT* Scan Counter Figure 4-11. Typical Posttriggered Acquisition © National Instruments Corporation 4-27 PCI-MIO E Series User Manual...

  • Page 72: Scanclk Signal

    Figure 4-13 shows the timing for the SCANCLK signal. CONVERT* SCANCLK t d = 50 to 100 ns t w = 400 to 500 ns Figure 4-13. SCANCLK Signal Timing PCI-MIO E Series User Manual 4-28 © National Instruments Corporation...

  • Page 73: Extstrobe* Signal

    TRIG1 signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions. The PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-MIO-16XE-10 support analog triggering on the PFI0/TRIG1 pin. See Chapter 3, Hardware Overview, for more information on analog triggering. © National Instruments Corporation 4-29 PCI-MIO E Series User Manual...

  • Page 74: Figure 4-15. Trig1 Input Signal Timing

    In most pretriggered applications, the TRIG1 signal is generated by a software trigger. Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered DAQ operation. PCI-MIO E Series User Manual 4-30 © National Instruments Corporation...

  • Page 75: Trig2 Signal

    Figures 4-17 and 4-18 show the input and output timing requirements for the TRIG2 signal. Rising-edge polarity Falling-edge polarity t w = 10 ns minimum Figure 4-17. TRIG2 Input Signal Timing © National Instruments Corporation 4-31 PCI-MIO E Series User Manual...

  • Page 76: Startscan Signal

    This output is set to tri-state at startup. Figures 4-19 and 4-20 show the input and output timing requirements for the STARTSCAN signal. PCI-MIO E Series User Manual 4-32 © National Instruments Corporation...

  • Page 77: Figure 4-19. Startscan Input Signal Timing

    Start of Scan Start Pulse CONVERT* STARTSCAN t off t off = 10 ns minimum b. Scan in Progress, Two Conversions per Scan Figure 4-20. STARTSCAN Output Signal Timing © National Instruments Corporation 4-33 PCI-MIO E Series User Manual...

  • Page 78: Convert* Signal

    50 to 100 ns. This output is set to tri-state at startup. Figures 4-21 and 4-22 show the input and output timing requirements for the CONVERT* signal. PCI-MIO E Series User Manual 4-34 © National Instruments Corporation...

  • Page 79: Figure 4-21. Convert* Input Signal Timing

    CONVERT* signal are inhibited unless they occur within a DAQ sequence. Scans occurring within a DAQ sequence may be gated by either the hardware (AIGATE) signal or software command register gate. © National Instruments Corporation 4-35 PCI-MIO E Series User Manual...

  • Page 80: Aigate Signal

    23 ns high or low. There is no minimum frequency limitation. Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source. Figure 4-23 shows the timing requirements for the SISOURCE signal. PCI-MIO E Series User Manual 4-36 © National Instruments Corporation...

  • Page 81: Waveform Generation Timing Connections

    50 to 100 ns. This output is set to tri-state at startup. Figures 4-24 and 4-25 show the input and output timing requirements for the WFTRIG signal. © National Instruments Corporation 4-37 PCI-MIO E Series User Manual...

  • Page 82: Update* Signal

    The selected edge of the UPDATE* signal updates the outputs of the DACs. In order to use UPDATE*, you must set the DACs to posted-update mode. PCI-MIO E Series User Manual 4-38 © National Instruments Corporation...

  • Page 83: Figure 4-26. Update* Input Signal Timing

    The PCI-MIO E Series board UI counter normally generates the UPDATE* signal unless you select some external source. The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter. © National Instruments Corporation 4-39 PCI-MIO E Series User Manual...

  • Page 84: Uisource Signal

    Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source. General-Purpose Timing Signal Connections The general-purpose timing signals are GPCTR0_SOURCE, GPCTR0_GATE, GPCTR0_OUT, GPCTR0_UP_DOWN, GPCTR1_SOURCE, GPCTR1_GATE, GPCTR1_OUT, GPCTR1_UP_DOWN, and FREQ_OUT. PCI-MIO E Series User Manual 4-40 © National Instruments Corporation...

  • Page 85: Gpctr0_Source Signal

    23 ns high or low. There is no minimum frequency limitation. The 20 MHz or 100 kHz timebase normally generates the GPCTR0_SOURCE signal unless you select some external source. © National Instruments Corporation 4-41 PCI-MIO E Series User Manual...

  • Page 86: Gpctr0_Gate Signal

    TC and toggle output polarity on TC. The output polarity is software selectable for both options. This output is set to tri-state at startup. Figure 4-31 shows the timing of the GPCTR0_OUT signal. PCI-MIO E Series User Manual 4-42 © National Instruments Corporation...

  • Page 87: Gpctr0_Up_Down Signal

    1. This is true even if the source clock is being externally generated by another PFI. This output is set to tri-state at startup. Figure 4-32 shows the timing requirements for the GPCTR1_SOURCE signal. © National Instruments Corporation 4-43 PCI-MIO E Series User Manual...

  • Page 88: Gpctr1_Gate Signal

    1. This is true even if the gate is being externally generated by another PFI. This output is set to tri-state at startup. Figure 4-33 shows the timing requirements for the GPCTR1_GATE signal. PCI-MIO E Series User Manual 4-44 © National Instruments Corporation...

  • Page 89: Gpctr1_Out Signal

    This output is set to tri-state at startup. Figure 4-34 shows the timing requirements for the GPCTR1_OUT signal. GPCTR1_SOURCE GPCTR1_OUT (Pulse on TC) GPCTR1_OUT (Toggle output on TC) Figure 4-34. GPCTR1_OUT Signal Timing © National Instruments Corporation 4-45 PCI-MIO E Series User Manual...

  • Page 90: Gpctr1_Up_Down Signal

    The same timing diagram, but with the source signal inverted and referenced to the falling edge of the source signal, would apply when the counter is programmed to count falling edges. PCI-MIO E Series User Manual 4-46 © National Instruments Corporation...

  • Page 91: Freq_Out Signal

    1 through 16. The input clock of the frequency generator is software- selectable from the internal 10 MHz and 100 kHz timebases. The output polarity is software selectable. This output is set to tri-state at startup. © National Instruments Corporation 4-47 PCI-MIO E Series User Manual...

  • Page 92: Field Wiring Considerations

    For more information, refer to the application note, Field Wiring and Noise Consideration for Analog Signals, available from National Instruments. PCI-MIO E Series User Manual 4-48 © National Instruments Corporation...

  • Page 93: Calibration

    In the EEPROM there is a user-modifiable calibration area in addition to the permanent factory calibration area. This means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed. © National Instruments Corporation PCI-MIO E Series User Manual...

  • Page 94: Self-Calibration

    Your PCI-MIO E Series board can measure and correct for almost all of its calibration-related errors without any external signal connections. Your National Instruments software provides a self-calibration method. This self-calibration process, which generally takes less than a minute, is the preferred method of assuring accuracy in your application. Initiate self-calibration to minimize the effects of any offset, gain, and linearity drifts, particularly those due to warmup.

  • Page 95: Other Considerations

    See Appendix A, Specifications, for analog output gain error information. © National Instruments Corporation PCI-MIO E Series User Manual...

  • Page 97: Specifications

    (software-selectable per channel) Type of ADC.......... Successive approximation Resolution ..........12 bits, 1 in 4,096 Maximum sampling rate PCI-MIO-16E-1 ......1.25 MS/s multichannel PCI-MIO-16E-4 ......500 kS/s single-channel 250 kS/s multichannel © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 98 Overvoltage protection ......25 V powered on, 15 V powered off Inputs protected ......ACH<0..15>, AISENSE FIFO buffer size........512 S Data transfers ..........DMA, interrupts, programmed I/O DMA modes..........Scatter-gather Configuration memory size ....512 words PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 99 Amplifier Characteristics Input impedance Normal powered on......100 G in parallel with 100 pF Powered off........820 min. Overload.......... 820 min. Input bias current ........200 pA Input offset current......... 100 pA © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 100 90 dB 100 dB 95 dB 106 dB 100 dB Dynamic Characteristics Bandwidth Board Small Signal (-3 dB) Large Signal (1% THD) PCI-MIO-16E-1 1.6 MHz 1 MHz PCI-MIO-16E-4 600 kHz 350 kHz PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 101 System noise (LSBrms, not including quantization) Board Gain Dither Off Dither On PCI-MIO-16E-1 0.5 to 10 0.25 PCI-MIO-16E-4 0.5 to 5 0.15 10 to 20 0.35 Crosstalk..........-80 dB, DC to 100 kHz © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 102 Max update rate 1 channel..........1 MS/s 2 channel..........600 kS/s–1 MS/s (system-dependent) Type of DAC .........Double-buffered, multiplying FIFO buffer size PCI-MIO-16E-1.......2,048 S PCI-MIO-16E-4.......512 S Data transfers ..........DMA, interrupts, programmed I/O DMA modes..........Scatter gather PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 103 Current drive .......... 5 mA max Protection ..........Short-circuit to ground Power-on state........0 V External reference input Range ..........11 V Overvoltage protection....25 V powered on, 15 V powered off © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 104 Level ..........5.000 V ( 2.5 mV) (actual value stored in EEPROM) Temperature coefficient....5 ppm/ C max Long-term stability ......15 ppm/ 1, 000 h Digital I/O Number of channels........8 input/output Compatibility ..........TTL/CMOS PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 105 Frequency scaler ......10 MHz, 100 kHz Base clock accuracy ....... 0.01% Max source frequency ......20 MHz Min source pulse duration ..... 10 ns, edge-detect mode Min gate pulse duration ......10 ns, edge-detect mode © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 106 35 V when configured as an analog trigger signal or disabled, 35 V powered off Digital Trigger Compatibility ..........TTL Response ..........Rising or falling edge Pulse width..........10 ns min PCI-MIO E Series User Manual A-10 © National Instruments Corporation...

  • Page 107: Bus Interface

    (not including connectors) ....17.5 by 10.6 cm (6.9 by 4.2 in) I/O connector.......... 68-pin male SCSI-II type Environment Operating temperature......0 to 55 C Storage temperature ....... -55 to 150 C Relative humidity ........5% to 90% noncondensing © National Instruments Corporation A-11 PCI-MIO E Series User Manual...

  • Page 108: Input Characteristics

    Max working voltage......Each input should remain within 11 V of ground Overvoltage protection ......25 V powered on, 15 V powered off Inputs protected ......ACH<0..15>, AISENSE FIFO buffer size ........512 samples © National Instruments Corporation A-12 PCI-MIO E Series User Manual...
  • Page 109 Amplifier Characteristics Input impedance Normal, powered on......100 G in parallel with 100 pF Powered off........820 Overload.......... 820 Input bias current ........1 nA Input offset current......... 2 nA © National Instruments Corporation A-13 PCI-MIO E Series User Manual...
  • Page 110 0.7 LSBrms 1.1 LSBrms 1.1 LSBrms 2.0 LSBrms 2.0 LSBrms 3.8 LSBrms Dynamic range........91.7 dB, 10 V input with gain 1 to 10 Crosstalk ..........-70 dB max, DC to 100 kHz PCI-MIO E Series User Manual A-14 © National Instruments Corporation...
  • Page 111 Relative accuracy (INL)......0.5 LSB typ, 1 LSB max DNL ............1 LSB max Monotonicity .......... 16 bits, guaranteed Offset error After calibration ......305 V max Before calibration......20 mV max © National Instruments Corporation A-15 PCI-MIO E Series User Manual...
  • Page 112 Gain temperature coefficient ....7.5 ppm/ C Onboard calibration reference Level ..........5.000 V ( 2 mV) (actual value stored in EEPROM) Temperature coefficient....0.6 ppm/ C max Long-term stability ......6 ppm/ 1, 000 h PCI-MIO E Series User Manual A-16 © National Instruments Corporation...

  • Page 113: Number Of Channels

    Counter/timers......... 24 bits Frequency scaler ......4 bits Compatibility ......... TTL/CMOS Base clocks available Counter/timers......... 20 MHz, 100 kHz Frequency scaler ......10 MHz, 100 kHz Base clock accuracy ....... 0.01% © National Instruments Corporation A-17 PCI-MIO E Series User Manual...

  • Page 114: Resolution

    35 V when configured as an analog signal or disabled; 35 V powered off Accuracy ..........1% of fullscale range Digital Trigger Compatibility ..........TTL Response ..........Rising or falling edge Pulse width..........10 ns min PCI-MIO E Series User Manual A-18 © National Instruments Corporation...
  • Page 115 (not including connectors) ....33.8 by 9.9 cm (13.3 by 3.9 in) I/O connector.......... 68-pin male SCSI-II type Environment Operating temperature......0 to 55 C Storage temperature ....... -55 to 150 C Relative humidity ........5% to 90% noncondensing © National Instruments Corporation A-19 PCI-MIO E Series User Manual...

  • Page 116: Type Of Dac

    8 V of ground, and each input should remain within 11 V of ground. Overvoltage protection ......25 V powered on, 15 V powered off Inputs protected ......ACH<0..15>, AISENSE FIFO buffer size ........2,048 samples © National Instruments Corporation A-20 PCI-MIO E Series User Manual...

  • Page 117: Dnl

    Input offset current......... 20 nA CMRR, DC to 60 Hz Gain = 1 .......... 80 dB Gain = 2 .......... 86 dB Gain = 10 ........100 dB Gain = 100 ........120 dB © National Instruments Corporation A-21 PCI-MIO E Series User Manual...
  • Page 118 Long-term stability ......15 ppm/ 1, 000 h Analog Output Output Characteristics Number of channels........2 Resolution ..........12 bits, 1 in 4,096 Max update rate ........20 kS/s Type of DAC .........Double-buffered PCI-MIO E Series User Manual A-22 © National Instruments Corporation...

  • Page 119: Monotonicity

    50 s Slew rate..........2 V/ s Noise ............40 Vrms, DC to 1 MHz Glitch energy (at midscale transition) Magnitude ........30 mV Duration .......... 10 s © National Instruments Corporation A-23 PCI-MIO E Series User Manual...
  • Page 120 Output high voltage = 13 mA) 4.35 V — Power-on state ........Input (High-Z) Data transfers ..........Programmed I/O Timing I/O Number of channels........2 up/down counter/timers, 1 frequency scaler Resolution Counter/timers .........24 bits PCI-MIO E Series User Manual A-24 © National Instruments Corporation...
  • Page 121 Trigger Lines.......... 7 Bus Interface Type ............Master, slave Power Requirement +5 VDC ( 5%)........1.0 A Power available at I/O connector ... +4.65 to +5.25 VDC at 1 A © National Instruments Corporation A-25 PCI-MIO E Series User Manual...
  • Page 122 (not including connectors) ....17.5 by 9.9 cm (6.9 by 3.9 in) I/O connector ..........68-pin male SCSI-II type Environment Operating temperature ......0 to 55 C Storage temperature ........-55 to 150 C Relative humidity........5% to 90% noncondensing PCI-MIO E Series User Manual A-26 © National Instruments Corporation...
  • Page 123 Figure B-1 shows the pin assignments for the 68-pin MIO connector. This connector is available when you use the SH6868 or R6868 cable assemblies with the PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-MIO-16XE-10, and PCI-MIO-16XE-50. © National Instruments Corporation PCI-MIO E Series User Manual...

  • Page 124: Figure B-1. 68-Pin Mio Connector Pin Assignments

    PFI2/CONVERT* +5 V PFI3/GPCTR1_SOURCE DGND PFI4/GPCTR1_GATE PFI5/UPDATE* GPCTR1_OUT PFI6/WFTRIG DGND DGND PFI7/STARTSCAN PFI9/GPCTR0_GATE PFI8/GPCTR0_SOURCE GPCTR0_OUT DGND FREQ_OUT DGND Not available on PCI-MIO-16XE-10 or PCI-MIO-16XE-50 Figure B-1. 68-Pin MIO Connector Pin Assignments PCI-MIO E Series User Manual © National Instruments Corporation...

  • Page 125: Figure B-2. 50-Pin Mio Connector Pin Assignments

    +5 V SCANCLK EXTSTROBE* PFI0/TRIG1 PFI2/CONVERT* PFI1/TRIG2 PFI3/GPCTR1_SOURCE PFI4/GPCTR1_GATE GPCTR1_OUT PFI5/UPDATE* PFI6/WFTRIG PFI7/STARTSCAN PFI9/GPCTR0_GATE PFI8/GPCTR0_SOURCE FREQ_OUT GPCTR0_OUT Not available on the PCI-MIO-16XE-10 or PCI-MIO-16XE-50 Figure B-2. 50-Pin MIO Connector Pin Assignments © National Instruments Corporation PCI-MIO E Series User Manual...

  • Page 127: General Information

    2. What is the DAQ-STC? The DAQ-STC is the system timing control application-specific integrated circuit (ASIC) designed by National Instruments and is the backbone of the PCI-MIO E Series boards. The DAQ-STC contains seven 24-bit counters and three 16-bit counters. The counters are divided into three groups: •...

  • Page 128: Installation And Configuration

    What jumpers should I be aware of when configuring my PCI-MIO E Series board? The PCI-MIO E Series boards are jumperless and switchless. Which National Instruments document should I read first to get started using DAQ software? Your NI-DAQ or application software release notes documentation is always the best starting place.
  • Page 129 ND_PFI_5, ND_HIGH_TO_LOW) • If you are using LabVIEW, invoke AI Clock Config VI with clock source code set to PFI pin, high to low, and clock source string set to 5. © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 130 If you are using the NI-DAQ language interface or LabWindows/CVI, the answer is no, the counter/timer applications that you wrote previously will not work with the DAQ-STC. You must use the GPCTR functions; ICTR and CTR functions will not PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 131 Warning: If you enable a PFI line for output, do not connect any external signal source to it; if you do, you can damage the board, the computer, and the connected equipment. © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 132 Table 4-1 shows that there is a 50 k pull-up resistor. This pull-up resistor will set the DIO(0) pin to a logic high when the output is in a high impedance state. PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 133 Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24-hour support with a collection of files and documents to answer most common customer questions. From these sites, you can also download the latest instrument drivers, updates, and example programs. For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information, call (512) 795-6990.
  • Page 134 Fax and Telephone Support National Instruments has branch offices all over the world. Use the list below to find the technical support number for your country. If there is no National Instruments office in your country, contact the source from which you purchased your software to obtain support.
  • Page 135 National Instruments for technical support helps our applications engineers answer your questions more efficiently. If you are using any National Instruments hardware or software products related to this problem, include the configuration forms from their user manuals. Include additional pages if necessary.
  • Page 136 Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
  • Page 137 Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: PCI-MIO E Series User Manual Click here to comment on this document...
  • Page 139 Value pico- nano- micro- milli- kilo- mega- giga- Symbols/Numbers ˚ degrees > greater than greater than or equal to < less than less than or equal to percent plus or minus © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 140 ANSI American National Standards Institute analog output AOGND analog output ground signal ASIC Application-Specific Integrated Circuit—a proprietary semiconductor component designed and manufactured to perform a set of specific functions. PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 141 (timing) counter digital-to-analog digital-to-analog converter—an electronic device, often an integrated circuit, that converts a digital number into a corresponding analog voltage or current © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 142 1 LSB digital output EEPROM electrically erasable programmable read-only memory—ROM that can be erased with an electrical signal and reprogrammed EXTREF external reference signal EXTSTROBE external strobe signal PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 143 1 output signal GPCTR0_SOURCE general purpose counter 0 clock source signal GPCTR1_SOURCE general purpose counter 1 clock source signal GPCTR0_UP_DOWN general purpose counter 0 up down GPCTR1_UP_DOWN general purpose counter 1 up down © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 144 PCI-MIO E Series User Manual © National Instruments Corporation...
  • Page 145 PCs and work-stations; it offers a theoretical maximum transfer rate of 132 MB/s. Programmable Function Input PFI0/TRIG1 PFI0/trigger 1 PFI1/TRIG2 PFI1/trigger 2 PFI2/CONVERT* PFI2/convert PFI3/GPCTR1_SOURCE PFI3/general purpose counter 1 source PFI4/GPCTR1_GATE PFI4/general purpose counter 1 gate © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 146 RTSIbus real-time system integration bus—the National Instruments timing bus that connects DAQ boards directly, by means of connectors on top of the boards, for precise synchronization of functions...
  • Page 147 The junction produces a small voltage as a function of the temperature. TRIG trigger signal © National Instruments Corporation PCI-MIO E Series User Manual...
  • Page 148 (VI), which consists of a front panel user interface and a block diagram program volts, input high volts, input low volts in measured voltage volts, output high volts, output low reference voltage Vrms volts, root mean square PCI-MIO E Series User Manual G-10 © National Instruments Corporation...
  • Page 149 Glossary waveform multiple voltage readings taken at a specific sampling rate WFTRIG waveform generation trigger signal © National Instruments Corporation G-11 PCI-MIO E Series User Manual...
  • Page 151 I/O signal summary (table) signal connections, 4-22 to 4-23 PCI-MIO-16E-1 and specifications PCI-MIO-16E-4, 4-6 PCI-MIO-16E-1 and PCI-MIO-16XE-10, 4-7 PCI-MIO-16E-4, A-6 to A-8 PCI-MIO-16XE-50, 4-9 PCI-MIO-16XE-10, A-15 to A-16 PCI-MIO-16XE-50, A-22 to A-24 © National Instruments Corporation I -1 PCI-MIO E Series User Manual...
  • Page 152 1-6 to 1-7 PCI-MIO-16E-1 and PCI-MIO-16E-4, customer communication, xiv, D-1 to D-2 A-11 PCI-MIO-16XE-10, A-19 PCI-MIO-16XE-50, A-25 DAC0OUT signal analog output connections, 4-22 to 4-23 description (table), 4-3 PCI-MIO E Series User Manual I -2 © National Instruments Corporation...
  • Page 153 (figure), 3-9 DIFF (differential) input mode documentation definition (table), 3-4 conventions used in manual, xii to xiii description, 4-15 National Instruments documentation set, ground-referenced signal sources, 4-16 xiii to xiv © National Instruments Corporation I -3 PCI-MIO E Series User Manual...
  • Page 154 GPCTR1_SOURCE signal, 4-43 to 4-44 PCI-MIO-16XE-10, 4-8 GPCTR1_UP_DOWN signal, 4-46 to PCI-MIO-16XE-50, 4-10 4-47 timing connections, 4-29 glitches, 3-12 GPCTR0_GATE signal, 4-42 GPCTR0_OUT signal fax and telephone support, D-2 description (table), 4-5 PCI-MIO E Series User Manual I -4 © National Instruments Corporation...
  • Page 155 4-17 to 4-18 considerations, 3-9 to 3-10 ground-referenced signal sources, range selection considerations, 3-7 4-16 analog output, 3-11 to 3-12 nonreferenced signal sources, 4-17 to 4-18 polarity selection, 3-11 to 3-12 © National Instruments Corporation I -5 PCI-MIO E Series User Manual...
  • Page 156 I/O, C-4 to C-6 68-pin MIO connector pin custom cabling, 1-6 to 1-7 assignments (figure), B-2 features, 1-1 to 1-2 pin assignments (figure), 4-2 installation, 2-1 to 2-2 PCI-MIO E Series User Manual I -6 © National Instruments Corporation...
  • Page 157 PCI-MIO-16E-4, 4-7 description (table), 4-5 PCI-MIO-16XE-10, 4-8 I/O signal summary (table) PCI-MIO-16XE-50, 4-10 PCI-MIO-16E-1 and PCI-MIO-16E-4, 4-7 PFI4/GPCTR1_GATE signal PCI-MIO-16XE-10, 4-8 description (table), 4-4 PCI-MIO-16XE-50, 4-10 I/O signal summary (table) © National Instruments Corporation I -7 PCI-MIO E Series User Manual...
  • Page 158 3-11 to 3-12 3-19 posttriggered data acquisition, 4-27 specifications illustration, 4-27 PCI-MIO-16E-1 and power connections, 4-25 PCI-MIO-16E-4, A-11 power requirements PCI-MIO-16XE-10, A-19 PCI-MIO-16E-1 and PCI-MIO-16E-4, PCI-MIO-16XE-50, A-25 A-11 PCI-MIO E Series User Manual I -8 © National Instruments Corporation...
  • Page 159 GPCTR1_GATE signal, 4-44 to (warning), 4-1 4-45 I/O signal summary (table) GPCTR1_OUT signal, 4-45 PCI-MIO-16E-1 and GPCTR1_SOURCE signal, 4-43 PCI-MIO-16E-4, 4-6 to 4-7 to 4-44 PCI-MIO-16XE-10, 4-7 to 4-9 © National Instruments Corporation I -9 PCI-MIO E Series User Manual...
  • Page 160 PCI-MIO-16XE-10, A-15 to A-16 PCI-MIO-16XE-10, A-18 PCI-MIO-16XE-50, A-22 to A-24 PCI-MIO-16XE-50, A-25 bus interface stability PCI-MIO-16E-1 and analog input PCI-MIO-16E-4, A-11 PCI-MIO-16E-1 and PCI-MIO-16XE-10, A-19 PCI-MIO-16E-4, A-6 PCI-MIO-16XE-50, A-25 PCI-MIO-16XE-10, A-15 PCI-MIO E Series User Manual I -10 © National Instruments Corporation...
  • Page 161 (figure), 4-30 GPCTR0_SOURCE signal, 4-41 output timing (figure), 4-30 GPCTR0_UP_DOWN signal, 4-43 TRIG2 signal, 4-31 to 4-32 GPCTR1_GATE signal, 4-44 to 4-45 input timing (figure), 4-31 GPCTR1_OUT signal, 4-45 © National Instruments Corporation I -11 PCI-MIO E Series User Manual...
  • Page 162 PCI-MIO E Series, 1-7 UPDATE* signal, 4-38 to 4-40 input timing (figure), 4-39 output timing (figure), 4-39 VCC signal PCI-MIO-16E-1 and PCI-MIO-16E-4, PCI-MIO-16XE-10, 4-7 PCI-MIO-16XE-50, 4-9 VirtualBench application software, 1-3 PCI-MIO E Series User Manual I -12 © National Instruments Corporation...

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