LG 42LC7D Service Manual page 39

ARM CPU/EEPROM
3.3VDD_CPU
2.5VDD_CPU
LDATA[13] DATA13
121
LDATA[12] DATA12
122
LDATA[11] DATA11
123
LDATA[10] DATA10
124
0.1uF C100 VDDIO3
125
VSSIO5
126
LDATA[9]
DATA9 127
LDATA[8]
DATA8 128
LDATA[7]
DATA7 129
LDATA[6]
DATA6 130
LDATA[5]
DATA5 131
LDATA[4]
DATA4 132
LDATA[3]
DATA3 133
LDATA[2]
DATA2 134
LDATA[1]
DATA1 135
LDATA[0]
DATA0 136
LADDR[24]
ADDR24/GPA9 137 IC100
LADDR[23] & 0.1uF C101
For applying the OAD VDD5 138
LADDR[24]
VSS5 139
LADDR[23]
ADDR23/GPA8 140
LADDR[22]
ADDR22/GPA7 141
LADDR[21]
ADDR21/GPA6 142
LADDR[20]
ADDR20/GPA5 143 S3C44BOX01-EDRO
LADDR[19]
ADDR19/GPA4 144
LADDR[18]
ADDR18/GPA3 145
LADDR[17]
ADDR17/GPA2 146
LADDR[16]
ADDR16/GPA1 147
LADDR[15]
ADDR15 148
LADDR[14]
ADDR14 149
LADDR[13] $ 4.42
ADDR13
150
LADDR[12] ADDR12
151
VSSIO6
152
LADDR[11] ADDR11
153
LADDR[10] ADDR10
154
LADDR[9] ADDR9
155
LADDR[8] ADDR8
156
LADDR[7] ADDR7
157
LADDR[6] ADDR6
158
LADDR[5] ADDR5
159
LADDR[4] ADDR4
160
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
CPLD/UART/RESET/HUB
3.3VDD_CPLD
+3.3V 3.3VDD_CPLD
L300
4.7K R3075 JP6
MLB-201209-0120P-N2 EPLD_TDI
C300 C302 4.7K R3076 JP7
C301 EPLD_TMS
0.01uF
47uF 16V 0.1uF 4.7K R3077 JP8
EPLD_TCK
JP9
4.7K R3078
EPLD_TDO
C348
100pF
C349 100pF
3.3VDD_CPLD
C309 C310
OPT OPT
CPU or MICOM SEL
0 R3003
I2C_HUB_EN4
0 R3004
I2C_HUB_EN3
0 R3005
I2C_HUB_EN2
0 R3006
I2C_HUB_EN1
I2C_HUB0
I2C_HUB1
C303
0.1uF
VCCIO 109 72 GND
0 R3002
I/O 110 71 I/O
I/O 111 70 I/O
I/O 112 69 I/O
I/O 113 68 I/O
GND 114 IO4_6 50 IO3_4 67 TCK
76
I/O 115 IO4_7 49 IO3_3 66 I/O
77
I/O 116 IO4_14 48 TCK 65 TMS
78
I/O 117 IC300 64 I/O
IO4_18 79 47 TMS
I/O 118 63 TDI
DET_SPDIF NC9 80 46 NC7
I/O 119 62 GND
CV_SYNC_MODE1 IO4_10 81 45 TDI
I/O 120 XC95288XL-10TQ 61 I/O
CV_SYNC_MODE0 IO4_12 82 44 GND3
I/O 121 60 I/O
TDO 83 43 NC6
22 R3007 TDO 122 $1.93 59 I/O
EPLD_TDO GND7 84 42 IO3_9
GND 123 58 I/O
IO4_13 85 41 IO3_1
I/O 124 57 I/O
CH_STRB IO4_16 86 40 IO1_18
I/O 125 56 I/O
CH_CS IO2_1 87 39 IO1_16
I/O 126 55 VCCIO
CPU_OE 0.1uF C304 VCCIO_2.5V/3.3V_4 88 VCCIO_2.5V/3.3V_2 38
VCCIO 127 I/O
IO4_15 89 37 IO3_8 54
I/O 128 I/O
CPU_WE IO4_17 90 36 IO1_13 53
I/O 129 I/O
CPU_WAIT IO2_3 91 35 IO3_5 52
R3000 I/O 130 I/O
CH_WR IO2_18 92 IC305 34 NC5 51
OPT 22 R3008 I/O 131 50 I/O
0 IO2_4 93 33 IO1_12
R3009 I/O 132 49 I/O
HC_RDY 0 IO2_2 94 32 IO3_2
R3010 I/O 133 XC9572XL-10TQ100C 48 I/O
0 IO2_5 95 31 GND2
R3011 I/O 134 47 GND
IO2_6 96 OPT 30 IO1_17
22 R3012 I/O 135 46 I/O
RX_HDMI_SPDIF IO2_8 97 29 IO1_15
22 R3013 I/O 136 $0.8 I/O
HD2_ICE958_OUT VCCINT_3.3V_3 98 28 IO1_10 45
22 R3014 I/O 137 I/O
PWR_DOWN IO2_9/GSR 99 27 IO1_14/GCK3 44
22 R3015 I/O 138 I/O
SPDIF_BYPASS_SEL GND8 100 VCCIO_2.5V/3.3V_1 26 43
22 R3016 I/O 139 42 VCCINT
CPU_CLKOUT
I/O
HD2_SPDIF_CLK OPT R3017 I/O 140 41
0.1uF C305 I/O
VCCINT 141 40
I/O
SPDIF_OUT 22 R3018 I/O 142 39
38 I/O/GCK3
SYS_RESET 22 R3019 I/O/GSR 143
37 VCCIO
GND 144
OPT R3035
C312 C313 C314
OPT OPT OPT
CPLD
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.3V
+3.3V 3.3VDD_CPU
L100
FLASH_DOWN MLB-201209-0120P-N2
C C113 C114 C115
47uF 0.01uF
B Q100 0.1uF
2SC3875S 16V
E +3.3V
3.3VDD_CPU
$ 0.06
IC102
MIC39100
SIGN101764
VIN 1 3 VOUT
2
C126 GND C127
C125
22uF
35V
0.1uF 0.1uF
3.3VDD_CPU
AR175
4.7K
DQM0/WBE0
DQM1/WBE1
DQM2/WBE2
DQM3/WBE3
80 AIN5
AR176
79 AIN4
4.7K
78 AIN3 R149
22
77 AIN2 R150 CPU_OE
22
76 AIN1 CPU_WE
75 AIN0 OPT R151 FLASH_CS
74 VSSADC
CH_CS
73 VSSIO3
72 TOUT4/VD7/GPE7 1K R146 3.3VDD_CPU
HDMI0_HPD
71 TOUT3/VD6/GPE6 1K R152
HDMI1_HPD
70 TOUT2/TCLK/GPE5 0 R153
DET_SPDIF
69 TOUT1/TCLK/GPE4 0 R154
I2C_HUB1
68 TOUT0/GPE3 0 R155
I2C_HUB0
67 EXTCLK
EXTCLK 4.7K R177
66 PLLCAP CPU_WAIT
PLLCAP 4.7K R178
65 EXTAL0 EXTCLK
EXTAL0
64 XTAL0 4.7K R179
XTAL0 XDACK0
63 VSS3 OPT R184
CH_HD2_RESET
62 VDD3 0.1uF C111 PULL UP/DOWN & PLL CLK
61 IICSCL/GPF0 0 R156
CPU_SCL
60 IICSDA/GPF1 0 R157
CPU_SDA
59 SIOTXD/NRTS1/IISLRCK/GPF5
EPLD_TCK
58 SIORDY/TXD1/IISDO/GPF6
EPLD_TDO 3.3VDD_CPU
SIORXD/RXD1/IISDI/GPF7
57 EPLD_TDI
56 SIOCLK/NCTS1/IISCLK/GPF8
EPLD_TMS
55 ENDIAN/CODECLK/GPE8 0 R141
54 OM3 0 R142
53 OM2 0 R143
52 OM1 0 R144
51 OM0 0 R145
50 NRESET 0 R158
CPU_RESET
49 CLKOUT/GPE0 33 R147
CPU_CLKOUT
48 VSSIO2 C129
OPT
47 VDDIO2 0.1uF C112
46 TDO 0 R159 4.7K R196
CPU_TDO
45 TDI 0 R160
BST_TDI
44 TMS 0 R161
BST_TMS
43 TCK 0 R162
BST_TCK
42 NTRST 0 R163
BST_TRST
41 EXINT7/IISLRCK/GPG7 22 R164 HDMI_POWER1
BST_TRST
BST_TDI
BST_TMS
BST_TCK
CPU_TDO
R197
HD2_TDO
OPT
BOUNDARY SCAN TEST CONNECTOR
3.3VDD_CPU
IC101
AT24C512W-10SI-2.7
A0
1 8
A1
2 7
NC
3 6
GND
4 5
$ 0.85
CPU
G H
+3.3V
+3.3V
+3.3V
+3.3V R3129
OPT
C
OPT B KRC102S Q300
R3126
E
OPT SYS_RESET
R3127
OPT
R3128 CPU_RESET
C335 C337
OPT OPT
IC304
74HC14D
R3100 R3109
330 I O 100 A1 VCC
1 3 1 14
2 0
R3120 Y1 2 13 A6
G IC301
C331
C325 KIA7029AF 10uF A2 3 12 Y6
10uF
16V 0
16V R3121 Y2 4 11 A5
SYS_RESET
A3 5 10 Y5
0
R3122 Y3 6 9 A4
CPU_RESET
GND 7 8 Y4
H/W RESET
+5V_ST 3.3VST_MICOM
0 0.33uF C329
R3079 DVIRGB_HS_POL
22 R3080 EPLD_TCK
C334
IC303 47uF
22 R3081 EPLD_TMS 16V
ST3232CDR
22 R3082 0.047uF C326 C1+ 1 16 VCC
EPLD_TDI
C347 0.33uF V+ 2 15 GND
22 R3083
VH_FID 100
C1- T1OUT DEBUG_TxD0 R3132
3 14
22 R3084 100
VH_VS C2+ R1IN DEBUG_RxD0 R3133
22 R3085 4 13
VH_HS
10pF C322 0.33uF C327 C2- R1OUT C333 C336
5 12 330pF 330pF
OPT C323
V- T1IN
0.1uF C315 10pF C324 6 11
22 R3086 T2OUT T2IN
DVI_DE 7 10 0 R3123
22 R3087
DVI_VS R2IN R2OUT
22 R3088 8 9 0 R3124
DVI_HS
22 R3089 0
DVI_DE_OUT R3125
22 R3090 0
XDR_DE_OUT R3112
22 R3091
XDR_FID_OUT 0.33uF C330
22 R3092
XDR_DE_OUT2
15pF OPT R3093 CPU_RxD0
$ 0.38
C318 100 CPU_TxD0
XDR_CLK_OUT_CPLD
22 R3094
XDR_HS_OUT UCOM_RX
22 R3095
XDR_VS_OUT
0.1uF C316
R3096 OPT
22 AV1_S_SW
R3097 OPT
22 AV1_V_SW
R3098 OPT
22 AV2_V_SW
0.1uF C317
+5.0V +3.3V +3.3V +3.3V
IC302
PA9516APW
0
SCL0 VCC
CPU_SCL R3107 1 16
0 SDA0 EN4
CPU_SDA R3108 2 15
SCL1 SDA4
SCL_CH1 3 14
SDA1 SCL4
SDA_CH1 4 13
EN1 EN3
I2C_HUB_EN1 5 12
SCL2 SDA3
SCL_CH2 6 11
SDA2 SCL3
SDA_CH2 7 10
GND 8 9 EN2
$ 0.85
FLASH/SDRAM/0Delay BUF
LDATA[0-31]
LDATA[0-31]
LADDR[2-24]
2.5VDD_CPU
L101
LADDR[17]
MLB-201209-0120P-N2 LADDR[16]
C121 C123 C124 LADDR[15]
C128 0.01uF
47uF 0.1uF
16V +3.3V LADDR[14]
47uF
LADDR[13]
25V
LADDR[12]
LADDR[11]
LADDR[10]
LADDR[21]
LADDR[22]
R220
4.7K
LADDR[23]
R219
PLLCAP R220 R219
XTAL0 4MB 4.7K OPT
LADDR[20]
8MB OPT 0
LADDR[19]
LADDR[9]
R186
LADDR[8]
OPT
EXTAL0
LADDR[7]
C116 LADDR[6]
C118 C120
22pF 22pF 820pF
LADDR[5]
LADDR[4]
LADDR[3]
R209
0
FLASH_DOWN
CPU_WE
SYS_RESET
CPU_OE
FLASH_CS
LADDR[17]
LADDR[16]
LADDR[15]
+3.3V
LADDR[14]
LADDR[13]
LADDR[12]
LADDR[11]
LADDR[10]
LADDR[21]
LADDR[22]
R221
4.7K
OPT
LADDR[23] R222
R221 R222
4MB 4.7K OPT
8MB OPT 0
LADDR[20]
LADDR[19]
LADDR[9]
LADDR[8]
LADDR[7]
LADDR[6]
VCC LADDR[5]
LADDR[4]
WP
LADDR[3]
SCL R187 22
SCL_CH2
SDA R188 22
SDA_CH2
C117 C119 C122
0.1uF 270pF OPT
CPU MEMORY(FLASH/SDRAM)
EEPROM(64Kbyte)
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
HD-II 2.4
L
1.8V Regulator for HD2.4 Digital Power 1
+3.3V
+3.3V
IC400
AZ1117H-1.8TRE1(EH13A)
+1.8V_HD2_DIGITAL_D1
INPUT 3 1 ADJ/GND
2
OUTPUT
C400 C402 $0.06
10uF 0.1uF
25V
16V
L401
MLB-201209-0120P-N2
P300 C405 C407
0.1uF 10uF
GIL-G-06-S3T2 16V 25V
22 R3140 1
EPLD_TCK
22 R3141 2
EPLD_TDO
C345
3 1.8V Regulator for HD2.4 Digital Power 2
100pF
22 R3142 4
EPLD_TMS
22 R3143 5 +3.3V
EPLD_TDI
IC404
6
AZ1117H-1.8TRE1(EH13A)
+1.8V_HD2_DIGITAL_D2
INPUT 3 1 ADJ/GND
2
OUTPUT
C490 C492 $0.06
10uF 0.1uF
25V
16V
L404
MLB-201209-0120P-N2
C489 C491
0.1uF 10uF
16V 25V
CPLD_Download
+5.0V VH_TP/D1_VALID
VH_TP/D1_DATA[0]
VH_TP/D1_DATA[1] AR406
VH_TP/D1_DATA[2]
0
VH_TP/D1_DATA[3]
VH_TP/D1_DATA[4]
VH_TP/D1_DATA[5] AR407
VH_TP/D1_DATA[6] 0
VH_TP/D1_DATA[7]
VH_TP/D1_DATA[0-7]
10
5
9
LDATA[0-31]
4
8
3
7
2
6
1
KCN-DS-1-0088
CN300
22 R3136 EPLD_TCK
22 R3137 EPLD_TDO
22 R3138 EPLD_TMS
22 R3139 EPLD_TDI
3.3V Regulator for HD2.4
+6.0V
IC402
AZ1117H-3.3
RS232(UART) LADDR[1-12]
INPUT 3 1 ADJ/GND +3.3V_HD2
OUTPUT
C401 C403
22uF 0.1uF 2 $0.06 L400
35V 16V
MLB-201209-0120P-N2
C404 C406
22uF 0.1uF
35V 16V
+5.0V
HD2_TDO R400 22
R401 22
BST_TRST
R402 22
BST_TCK R403 22
I2C_HUB_EN4 BST_TMS
R404 22
CPU_TDO
SDA_CH4
FOR BOUNDARY SCAN TEST
SCL_CH4
I2C_HUB_EN3
SDA_CH3
SCL_CH3
I2C_HUB_EN2
+1.8V_HD2_DIGITAL_D2
I2C 2 TO 4 HUB
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
LDATA[0-31]
LADDR[2-24]
3.3VDD_FLASH 3.3VDD_SDRAM 3.3VDD_SDRAM
IC202
HY57V641620ETP-6
IC200
0.1uF C204 VDD1 VSS3
MX29LV320CTTC-70G 1 54
LDATA[0] DQ0 DQ15 LDATA[15]
2 53
0.1uF VDDQ1 C205 VSSQ4
A15 A16 LADDR[18] 3 52
1 48
LDATA[1] DQ1 DQ14 LDATA[14]
A14 BYTE# 4 51
2 47
LDATA[2] DQ2 DQ13 LDATA[13]
A13 GND_2 5 50
3 46
VSSQ1 VDDQ4 0.1uF C214
A12 Q15/A-1 LDATA[15] 6 49
4 45
LDATA[3] DQ3 DQ12 LDATA[12]
A11 Q7 LDATA[7] 7 48
5 44
LDATA[4] DQ4 DQ11 LDATA[11]
A10 Q14 LDATA[14] 8 47
6 43
0.1uF C206 VDDQ2 VSSQ3
A9 Q6 LDATA[6] 9 46
7 42
LDATA[5] DQ5 DQ10 LDATA[10]
A8 Q13 LDATA[13] 10 45
8 41
LDATA[6] DQ6 DQ9
A19 Q5 LDATA[5] 11 44
9 40
VSSQ2 VDDQ3
A20 Q12 LDATA[12] 12 43 0.1uF C215
10 39
LDATA[7] DQ7 DQ8
WE# Q4 LDATA[4] 13 42
11 38
VDD2 VSS2
RESET# VCC 0.1uF C207 14 41
12 37
OPT LDQM NC
NC Q11 LDATA[11] 15 40
0 13 36 DQM0/WBE0
WE UDQM
WP#/ACC Q3 LDATA[3] 16 39
14 35 CPU_WE
CAS CLK
RY/BY# Q10 LDATA[10] 17 38
15 34 SCAS
RAS CKE
A18 Q2 LDATA[2] 18 37
16 33 SRAS
CS A12
A17 Q9 LDATA[9] 19 36
17 32 SCS0
LADDR[22] BA0 A11 LADDR[13]
A7 Q1 LDATA[1] R211 0 20 35
18 31
LADDR[23] R212 BA1 A9 LADDR[11]
A6 Q8 LDATA[8] 0 R213 0 21 34
19 30
LADDR[12] A10/AP A8 LADDR[10]
A5 Q0 LDATA[0] 22 33
20 29
LADDR[2] A0 A7
A4 OE# 23 32
21 28
LADDR[3] A1 A6
A3 GND_1 24 31
22 27
LADDR[4] A2 A5
A2 CE# 25 30
23 26
LADDR[5] A3 A4
A1 A0 LADDR[2] 26 29
24 25
0.1uF C208 VDD3 VSS1
27 28
R214
LADDR[24] 0
R211 R213 R212 R214
8MB 0 0 OPT OPT
16MB OPT OPT 0 0
3.3VDD_FLASH 3.3VDD_SDRAM 3.3VDD_SDRAM
IC203
HY57V641620ETP-6
IC201 VDD1 VSS3
0.1uF C209 1 54
MX29LV320CTTC-70G LDATA[16] DQ0 DQ15
2 53
VDDQ1 VSSQ4
0.1uF C210 3 52
A15 A16 LADDR[18]
1 48 LDATA[17] DQ1 DQ14
4 51
A14 BYTE#
2 47 LDATA[18] DQ2 DQ13
5 50
A13 GND_2
3 46 VSSQ1 VDDQ4
6 49 0.1uF C216
A12 Q15/A-1 LDATA[31]
4 45 LDATA[19] DQ3 DQ12
7 48
A11 Q7 LDATA[23]
5 44 LDATA[20] DQ4 DQ11
8 47
A10 Q14 LDATA[30]
6 43 VDDQ2 VSSQ3
0.1uF C211 9 46
A9 Q6 LDATA[22]
7 42 LDATA[21] DQ5 DQ10
10 45
A8 Q13 LDATA[29]
8 41 LDATA[22] DQ6 DQ9
11 44
A19 Q5 LDATA[21]
9 40 VSSQ2 VDDQ3
12 43 0.1uF C217
A20 Q12 LDATA[28]
10 39 LDATA[23] DQ7 DQ8
13 42
WE# Q4 LDATA[20]
11 38 0.1uF C212 VDD2 VSS2
14 41
RESET# VCC
12 37 LDQM NC
DQM2/WBE2 15 40
0 NC Q11 LDATA[27]
13 36 WE UDQM
CPU_WE 16 39
WP#/ACC Q3 LDATA[19]
14 35 CAS CLK
SCAS 17 38
RY/BY# Q10 LDATA[26]
15 34 RAS CKE
SRAS 18 37
A18 Q2 LDATA[18]
16 33 CS A12
19 36
A17 Q9 LDATA[25] SCS0
17 32 LADDR[22] R215 0 BA0 A11 LADDR[13]
20 35
A7 Q1 LDATA[17] R216
18 31 LADDR[23] 0 R217 0 BA1 A9 LADDR[11]
21 34
A6 Q8 LDATA[24]
19 30 LADDR[12] A10/AP A8 LADDR[10]
22 33
A5 Q0 LDATA[16]
20 29 LADDR[2] A0 A7
23 32
A4 OE#
21 28 LADDR[3] A1 A6
24 31
A3 GND_1
22 27 LADDR[4] A2 A5
25 30
A2 CE#
23 26 LADDR[5] A3 A4
26 29
A1 A0 LADDR[2]
24 25 0.1uF C213 VDD3 VSS1
27 28
R218
LADDR[24] 0
R215 R217 R216 R218
8MB 0 0 OPT OPT
16MB OPT OPT 0 0
VH_HS
VH_VS
HS_TO_ADC
VH_FID
HD2_EXT_CLK R448 0
AD21
DVI_DE 1/16W EXT_HD
R408 5% AC21 EXT_VD
DVI_DE_OUT AE21
OPT ORG_HD
AF22 EXT_INFIELD
AF8
VH_C/B[0-9] EXT_CLK
AE22 EXT_DVI_DE
VH_C/B[0] AF26 EXT_DB0
VH_C/B[1] AE25
VH_C/B[0-9] EXT_DB1
VH_C/B[2] AF25 EXT_DB2
VH_C/B[3] AD24
EXT_DB3
VH_C/B[4] AE24 EXT_DB4
VH_C/B[5] AF24
AD23 EXT_DB5
VH_Y/G[0-9] VH_C/B[6] EXT_DB6
VH_C/B[7] AE23
AF23 EXT_DB7
VH_C/B[8] EXT_DB8
VH_C/B[9] AD22
VH_Y/G[0-9] EXT_DB9
VH_Y/G[0] AA24
EXT_DG0
VH_Y/G[1] AB26 EXT_DG1
VH_Y/G[2] AB25
EXT_DG2
VH_Y/G[3] AB24 EXT_DG3
VH_Y/G[4] AC26
EXT_DG4
VH_C/R[0-9] VH_Y/G[5] AC25 EXT_DG5
VH_Y/G[6] AC24 IC401
EXT_DG6
VH_Y/G[7] AD26 EXT_DG7
VH_Y/G[8] AD25
EXT_DG8
VH_Y/G[9] AE26 EXT_DG9
VH_C/R[0] W26 EXT_DR0
VH_C/R[1] W25
EXT_DR1
VH_C/R[2] W24 EXT_DR2
VH_C/R[3] W23
EXT_DR3
VH_C/R[0-9] VH_C/R[4] Y26 EXT_DR4
VH_C/R[5] Y25
EXT_DR5
VH_C/R[6] Y24 EXT_DR6
VH_C/R[7] Y23
EXT_DR7
VH_C/R[8] AA26 EXT_DR8
VH_C/R[9] AA25
EXT_DR9
R491
4.7K A2 LGDT1102F (HD2.4)
D1CLK
VH_TP/D1_CLK R499 0 A4 CHACLK(TP_STROB)
A12
B12 CHA_VALID
CHA_ERROR
TP_ERROR C12
TP_SOP C13 CHA_SOP/PESREQ
CHA/D1_0
B13
A13 CHA/D1_1
CHA/D1_2
A14
B14 CHA/D1_3
CHA/D1_4
C14
A15 CHA/D1_5
CHA/D1_6
B15 CHA/D1_7
(HD 2.4)
R493 4.7K A11 TP_PWM
AF20
VCR_PWM
MAIN_PWM AF21 MAIN_PWM
HD2_SYSCLK
V1 SYSCLK
0 R405
0 R406
1/16W J3 XREQ/AUDIO_REQ
0 1/16W 5% R407 J2
5% XSTRB/AUDIO_STROBE
1/16W K4 XDATA/AUDIO_DATA
LDATA[0-31] 5%
LDATA[0] B11 HOSTDATA0
C11
LDATA[1] HOSTDATA1
LDATA[2] D11 HOSTDATA2
A10
LDATA[3] HOSTDATA3
LDATA[4] B10 HOSTDATA4
LDATA[5] C10
D10 HOSTDATA5
LDATA[6] HOSTDATA6
LDATA[7] A9
B9 HOSTDATA7
LDATA[8] HOSTDATA8
LDATA[9] C9
D9 HOSTDATA9
LDATA[10] HOSTDATA10
LDATA[11] A8
B8 HOSTDATA11
LDATA[12] HOSTDATA12
LDATA[13] C8 $ 14.5
D8 HOSTDATA13
LDATA[14] HOSTDATA14
LDATA[15] C7
B4 HOSTDATA15
LDATA[16] HOSTDATA16
LDATA[17] C4 HOSTDATA17
B3
LDATA[18] HOSTDATA18
LDATA[19] A1 HOSTDATA19
B2
LDATA[20] HOSTDATA20
LDATA[21] C3 HOSTDATA21
B1
LDATA[22] HOSTDATA22
LDATA[23] C2 HOSTDATA23
C1
LDATA[24] HOSTDATA24
LDATA[25] D3 HOSTDATA25
D2
LDATA[26] HOSTDATA26
LDATA[27] D1 HOSTDATA27
E3
LDATA[28] HOSTDATA28
LDATA[29] E2 HOSTDATA29
E1
LDATA[30] HOSTDATA30
LADDR[1-12] LDATA[31] F4 HOSTDATA31
LADDR[1] F3 HOSTADDR1
LADDR[2] F2
F1 HOSTADDR2
LADDR[3] HOSTADDR3
LADDR[4] G4
G3 HOSTADDR4
LADDR[5] HOSTADDR5
LADDR[6] G2
G1 HOSTADDR6
LADDR[7] HOSTADDR7
LADDR[8] H4
H3 HOSTADDR8
LADDR[9] HOSTADDR9
LADDR[10] H2
H1 HOSTADDR10
+3.3V_HD2 LADDR[11] HOSTADDR11
LADDR[12] J4 HOSTADDR12
B7 HOSTREADYPOL
R409 R446 D7
10K 0 HOSTTYPE1
0 1/16W R447 D6 HOSTTYPE0 For ARM
A7
HC_RDY 1/16W 5% HOSTREADY
5% A6 HOSTWR
CH_WR B6
CH_CS HOSTCS
R492 22 C6 HOSTDSTB
CH_STRB R450 A5
HD2_DMAACK1 OPT DMAACK
B5 DMAREQ
HC_DREQ R411 0 C5
HC_IRQ 100 IRQ
R412 A3 HOSTCLK
CPU_CLKOUT R451 0
HD2_DMAACK2
C15 TDO
A16
TRST
B16 TCK
C16
TMS
D16 TDI
T4
T3 TESTSE
TESTMODE0
U3
U4 TESTMODE1
TESTMODE2
1.8V Digital Power 1.8V Digital Ground 3.3V Digital Power
+1.8V_HD2_DIGITAL_D1
16V
LDATA[9]
LDATA[8]
+3.3V 3.3VDD_FLASH
DQM1/WBE1
L200
SCLK
MLB-201209-0120P-N2
SCKE
C218 C222
C220
0.01uF
47uF 16V 0.1uF
LADDR[9]
LADDR[8]
LADDR[7]
LADDR[6]
+3.3V 3.3VDD_SDRAM
L201
MLB-201209-0120P-N2
C219 C221 C223
0.1uF 0.01uF
47uF 16V
LDATA[31]
LDATA[30]
LDATA[29]
LDATA[28]
LDATA[27]
LDATA[26]
LDATA[25]
LDATA[24]
DQM3/WBE3
SCLK
SCKE
LADDR[9]
LADDR[8]
LADDR[7]
LADDR[6]
OPT R210
VH_EXT_CLK HD2_EXT_CLK
0Delay BUF
HD2_MEM_DATA[0-63]
HD2_MEM_DATA[0-63]
HD2_MEM_BA1
HD2_MEM_BA0
HD2_MEM_CS 1.8V Regulator for HD2.4 Analog Power
HD2_MEM_WE
HD2_MEM_RAS
HD2_MEM_CAS
HD2_MEM_CLK2
HD2_MEM_CLK1 +3.3V
HD2_MEM_ADDR[0-11]
HD2_MEM_ADDR[0-11]
IC403
AZ1117H-1.8TRE1(EH13A)
+1.8V_HD2_ANALO G
INPUT 3 1 ADJ/GND
2
OUTPUT
C484 C485
22uF 0.1uF
16V 16V
L402
MLB-201209-0120P-N2
C486 C487
0.1uF 47uF
16V 16V
AR400 XDR_DATA_G[0-9]
AE20 22 XDR_DATA_G[9]
DOUT_G13
AC19 XDR_DATA_G[8]
DOUT_G12 AD19 XDR_DATA_G[7]
DOUT-G11
AE19 XDR_DATA_G[6]
DOUT_G10 AF19 AR401 22 XDR_DATA_G[5]
DOUT_G9
AC18 XDR_DATA_G[4]
DOUT_G8 AD18 XDR_DATA_G[3]
DOUT_G7 AE18
XDR_DATA_G[2]
DOUT_G6 AF18 R415 22 XDR_DATA_G[1]
DOUT_G5 AC17 R416 22
DOUT_G4 XDR_DATA_G[0]
AD17
DOUT_G3 AE17
DOUT_G2
AF17
VCR_D1_DATA5/DOUT_G1 AD16
VCR_D1_DATA4/DOUT_GO XDR_DATA_R[0-9]
AE16 AR402 22
DOUT_R13 XDR_DATA_R[9]
AF16 XDR_DATA_R[8]
DOUT_R12 AD15
DOUT_R11 XDR_DATA_R[7]
AE15 XDR_DATA_R[6]
DOUT_R10 AF15 AR403
DOUT_R9 22 XDR_DATA_R[5]
AF14 XDR_DATA_R[4]
DOUT_R8 AE14
DOUT_R7 XDR_DATA_R[3]
AD14 XDR_DATA_R[2]
DOUT_R6 AF13 R413 22
DOUT_R5 XDR_DATA_R[1]
AE13 R414 22 XDR_DATA_R[0]
DOUT_R4 AD13
DOUT_R3 +1.8V_HD2_ANALOG
AF12 XDR_DATA_B[0-9]
DOUT_R2 AE12
VCR_D1_DATA1/DOUT_R1
AD12
VCR_D1_DATA0/DOUT_R0 +3.3V_HD2
AR404
AF11 22 XDR_DATA_B[9]
DOUT_B13 AE11 XDR_DATA_B[8]
DOUT_B12
AD11 XDR_DATA_B[7]
DOUT_B11 AF10 XDR_DATA_B[6]
DOUT_B10
AE10 AR405 22 XDR_DATA_B[5]
DOUT_B9 AD10 XDR_DATA_B[4]
DOUT_B8 AC10
XDR_DATA_B[3]
DOUT_B7 AF9 XDR_DATA_B[2]
DOUT_B6 AE9 R417 22
DOUT_B5 XDR_DATA_B[1]
AD9 R418 22 XDR_DATA_B[0] C467 C483
DOUT_B4 AC9 10uF C493
DOUT_B3 25V 10uF 0.1uF
AD8 25V 16V
DOUT_B2 AC8
VCR_D1_DATA3/DOUT_B1
AC7
VCR_D1_DATA2/DOUT_B0
R432
AD20 0
VCR_D1_DATA6 AC20 XDR_CLK_OUT_LVDS
VCR_D1_DATA7
AE6
DOUT_DE R431 33 XDR_DE_OUT
AF7
DOUT_CLK AE7
DOUT_HACTIVE R433 33 XDR_HS_OUT
AD7 R434 33 XDR_VS_OUT R452
DOUT_VACTIVE AF6 0
DOUT_FIELD R435 22 XDR_FID_OUT XDR_CLK_OUT_CPLD
AE8 HD2_NT2CLK
NT2CLK U1
VDPCLK HD2_VDPCLK
AE5
DAC_AVSSB AE4
AVSSIO_CVBS
AE3
3.3V Analog Ground DAC_AVSSG AE2
DAC_AVSSR AC3
DAC_VSSG AB3
DAC_AVSS
AD5 C469 0.01uF
DAC_AVD33B AD4
AVDDIO_CVBS C470 0.01uF
AD3 C471 0.01uF
DAC_AVD33G AD2
3.3V Analog Power DAC_AVD33R C472 0.01uF
AC2 C473 0.01uF
DAC_AVD33 AC1
DAC_VDDG C474 0.01uF
AC6
DVSS_DAC
AB2
AVSSIO_PLL AA4
PLL_AVSS
AA3
1.8V Analog Ground PLL_DVSS Y4
AUPLL_AVSS2
Y3
AUPLL_DVSS W4
AUPLL_AVSS
W3
AVSSIO_AUPLL
AD6 C475 0.01uF
DVDD_DAC AB1 C476
AVDDIO_PLL 0.01uF
AA2 C477 0.01uF
PLL_AVDD AA1 C478 0.01uF
1.8V Analog Power PLL_DVDD
Y2 C479 0.01uF
AUPLL_AVDD2 Y1 C480 0.01uF
AUPLL_DVDD
W2 C481 0.01uF
AUPLL_AVDD W1 C482 0.01uF
AVDDIO_AUPLL
AF5
SVIDEO_C
AF4
SVIDEO_Y
AF3 DTV_CVBS
CVBS_OUT
AF1 C464 0.01uF
COMP AE1
R436 182
RSET AF2 C465 0.01uF
VREFOUT AD1
VREFIN R437 OPT
+3.3V_HD2
T1
AUDCLK R1 R498 33
SPDIF_CLK T2 HD2_SPDIF_CLK
C488 HD2_DAC_MCLK
AUDCLK_OUT V2 R494 OPT FSEL
SYNCLK V4
FSEL 4.7K
Low : MEMCLK=135MHz
U2
EXT_RESETN HD2_RESET
High : MEMCLK=162MHz
+3.3V_HD2
R495
4.7K
R3 R423 22
EXT_DAC_LRCK HD2_DAC_LRCLK
R2 R424 22 HD2_DAC_SCLK
EXT_DAC_SCK N1 R425 22
IEC958_OUT HD2_ICE958_OUT
M1 R426 0 HD2_ICE958_IN
IEC958LRCH M2 R420 OPT
CDLRCH M3
R421 1K TO MSP4440
CDLRCK L1 R422 1K
CDSCK P3 R427
DACLRCH 22 HD2_DAC_LRCH
P2
DACSLRCH P1 +3.3V_HD2
DACCLFCH R496
N3 4.7K
DACSELLRCH N2
DACHLRCH
L2 R428 22
LINELRCH L3 R429 AUDIO_IN_DATA_H
LINELRCK 0 AUDIO_IN_LRCLK FROM MSP4440
K1 R430 0
LINESCK K2 R497 OPT AUDIO_IN_SCLK
MICLRCH
K3
MICLRCK J1
MICSCK
V3 R444 OPT PWR_DOWN
STANDBYMODE
3.3V Digital Ground
+3.3V_HD2