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Model 5304A
Theory of Operation
S E C T I O N IX D
5 3 0 4 A T I M E R / C O U N T E R
S U B S E C T I O N I V
T H E O R Y O F O P E R A T I O N
9 D - 4 - 1 . INTRODUCTION
9D-4-2.
This subsection describes the theory of
operation for the 5304A Timer/Counter.
Basic oper-
ation of gates, certain amplifiers and
integrated
circuits is found in Section IV of the 5300A portion
of the manual.
9D-4-3.
To simplify measurement making refer to
operating information starting with Paragraph 9D-3-1
for optimum adjustment of various controls.
9 D - 4 - 4 . I N P U T AMPLIFIERS A N I ) MODES
O F OPERATION
9D-4-5. CHANNEL A. The Channel A input signal
is applied to front-panel INPUT A jack and attenu-
ated by A2 attenuator assembly (XI, X10, X100)
and sent to Al Channel A input amplifier.
The
A2 Attenuator Board Assembly also contains the
AC-DC switches, SLOPE switches, and the LEVEL
controls for both channels. The input signal is sent
through A2 to the input of matched FET source-
follower pair, Q2 and Q4.
Diodes CR2, CR4 are
limiters for Q2 inputs.
9D-4-6.
One side of the FET source-follower pair
(Q2) receives the input signal from A2J2 and the
other side (Q4) is connected to LEVEL A trigger-
level control A2R9.
Q2 and Q4 are connected to
differential amplifier Q6 and Q8 respectively and
provides level shifting and gain of approximately
.3 for Channel A signals.
Resistor R20 is a dc
balance for differential amplifier Q6 and Q8.
9D-4-7.
The output from Q6, Q8 drives another
differential amplifier, U24B.
The U24B output is
shaped by Schmitt-Trigger U24A and level-shifted
(ECL to TTL) through U21B, Q12 combination.
The U21B expander output is used to obtain suf-
ficient signal swing to drive Q12.
9D-4-8. CHANNEL B. The Channel B input signal
is applied to front-panel INPUT B jack and attenu-
ated by A2 Attenuator Assembly (Xl, X10, XI00)
and sent to Al Channel B input amplifier. The A2
Attenuator assembly also contains the Channel B
coupling switches, slope switches and the Channel
B level control.
The Channel B signal is routed
through A2 to the input of matched F E T source-
follower pair Ql and Q3.
Diodes CRl, CR3 are
limiters for Ql inputs.
9D-4-9.
One side of the Channel B FET source-
follower pair (Ql) receives the input signal from
A2J1 and the other side (Q3) is connected to LEVEL
B trigger level control A2R10. Q5 and Q7 are con-
nected to differential amplifiers Qf> and Q7 re-
spectively and provide level-shifting and gain of
approximately .3 for Channel B signals.
Resistor
R19 is a dc balance for differential amplifier Q5
and Q7.
9D-4-10.
The output from Q5, Q7 drives another
differential amplifier U23B.
The U23B output is
shaped bv Schmitt-Trigger U23A and level-shifted
(ECL to TTL) through U21A, Q l l combination. The
U21A expander output is used to obtain sufficient
signal swing to drive Q l l .
9D-4-11. VOLTAGE REGULATION. Transistors Q9,
Q10 provide regulated, low-ripple dc power to the
amplifiers and time interval hold-off circuits.
9D-4-12.
SLOPE SELECTION.
Slope selection for
Channel A is accomplished by using U19C, U20C,
and U20I) in conjunction with A2S7. Slope selection
for Channel B is accomplished by using U19I),
U20D, and U20A in conjunction with A2S(>.
9D-4-13.
CHECK MODE.
In the CHECK mode,
the operation of the 5300A 10 MHz crystal oscillator
and counting logic and the 5304A gating logic is
verified.
When A2S1 is in CHK mode, ground is
applied to U18A(2), U18I)(12), and U13C(5).
The
10 MHz clock from the 5300A A1J1(16) is routed
through the 5304A AlPl(16) and sent to U12D(12).
The Channel A switch (U18B) and Channel B switch
(U18C), gate the 10 MHz clock signal through.
The
Channel A switch output is also gated through U12B
and U16B and is available as the Fl signal at
A1P1(5).
9D-4-14.
FREQ A MODE.
In
the frequency
measuring mode, with the "Function" switch S2 in
any
of
its
four frequency measuring
positions
(FREQ AUTO, .IS, IS, 10S) the Channel A input
signal is gated through "Channel A Slope Selection"
switch comprised of U19C, U20C, and U20B.
The
input signal is then routed through another "Channel
A" switch made up of U18A and U18B.
From
U18B(6) the Channel A input signal is gated through
U12B and U16B as the Fl signal to the 5300A
mainframe which controls the opening and closing
of the main gate.
The 10 MHz clock signal from
9D-4-1
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