Sanyo DC-DA1100 (XE) Service Manual page 9

IC BLOCK DIAGRAM & DESCRIPTION
IC102 LC78629E (DSP for a CD Player)
No. Symbol I/O Function description
Defect detection signal(DEF) input pin.
1 DEFI I
(Must be connected to 0V when unused.)
Test input pin. A pull-down resistor is built-in.
2 TAI I
Must be connected to 0V.
3 PDO O
External VCO control phase comparator output pin.
4 VVSS - Internal VCO ground pin.Must be connected to 0V.
PLL
PDO output current adjustment resistor
5 ISET AI
connection pin.
6 VVDD - Internal VCO power supply pin.
7 FR AI VCO frequency range adjustment.
8 VSS -
Digital system ground pin. Must be connected to 0V.
9 EFMO O EFM signal output pin.
Slice level
control
10 EFMIN I EFM signal input pin.
Test input pin. A pull down resistor is built in.
11 TEST2 I
Must be connected to 0V.
12 CLV+ O
Disk motor control output.
Can be set to three-value output by microprpcessor command.
13 CLV- O
Rough servo/phase control automatic switching monitor
output pin.
14 V/*P O
Outputs a high level during rough servo and a low level.
Track detection signal input pin. This is a Schmidt input.
15 HFL I
Tracking error signal input pin. This is a Schmidt input.
16 TES I
Tracking off output pin.
17 TOFF O
Tracking gain switching output pin.
18 TGL O
Increase the gain when low.
Track jump output.
19 JP+ O
Three-value output is also possible when specified by
microprocessor command.
20 JP- O
EMF data playback clock monitor pin.
21 PCK O
Output 4.3218MHz when the normal-speed playback phase
command.
Synchhronization signal detection output pin. Output a high
level when the synchronization signal detected from the EFM
FSEQ O
22
signal and the internaly generated synchronization signal range.
Peripheral circuitry 5V system power suply pin.
23 VDD -
General-purpose 1
24 CONT1 I/O
input/output pin.
General-purpose 2
25 CONT2 I/O
input/output pin.
General-purpose 3
CONT3 I/O
26
input/output pin.
General-purpose 4
27 CONT4 I/O
input/output pin.
General-purpose 5
28 CONT5 I/O
input/output pin.
De-emphasis monitor pin.
A high level indicates playback of a de-emphasis disk,
EMPH/
O
29
General-purpose 6 output pin.
CONT6
Rest to EMPH function.
C2 flag output pin.
30 C2F O
Digital output pin. (EIJA format)
31 DOUT O
Test input pin.
TEST3 I
32
A pull-down resistor is built in. Must be connected to 0V.
_
DEFI 1
_
TAI 2
_
PDO 3
_
VVSS 4
_
ISET 5
_
VVDD 6
_
FR 7
_
VSS 8
_
EFMO 9
_
EFMIN 10
_
TEST2 11
_
CLV+ 12
_
CLV- 13
_
V *P 14
_
HFL 15
_
TES 16
Incertitude
Incertitude
Controlled by serial data commands.
From the microprocessor.
Any of these that are unused must
be either set up as input pin and
connected to 0V, or set up as output
pin and left open.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Output pin
No. Symbol I/O
to rest
Test input pin.
-
33 TEST4 I
A pull-down resistor is built in. Must be connected to 0V.
General-purpose I/O command identification pin.
A pull-down resistor is built in.
Used operate similarly to LC78622E connected to open or 0V.
34 PCCL I
H ; Must be connected to general-purpose port command.
L ; Be able to all command control.
-
MUTEL/
35 O
CONT7
Lch
36 LVDD - one-bit
DAC
37 LCHO O
38 LVSS -
-
39 RVSS -
40 RCHO O
-
Rch
41 RVDD - one-bit
-
DAC
MUTER/
42 O
L output
CONT8
43 XVDD - Crystal oscillator power supply pin.
L output
44 XOUT O
Connections for a 16.934MHz crystal oscillating circuit
ground pin.
45 XIN I
-
46 XVSS - Crystal oscillator ground pin. Must be connected to 0V.
-
Subcode block synchronization signal pin.
47 SBSY O
H output
48 O C1,C2,signal and double error correction monitor pin.
EFLG
49 O Subcode P,Q,R,S,T,U,V and W output pin.
PW
Subcode frame synchronization signal output pin.
50 SFSY O
L output
This signal falls when the subcode are in the standby stase.
Subcode readout clock input pin. This is a Schmitt input.
51 SBCK I
(Must be connected to 0V when unused.)
L output
Output for the 7.35kHz synchronization signal divided from
52 FSX O
the crystal oscillator pin.
Subcode Q output standby output pin.
53 WRQ O
Incertitude
54 I Read/ write control input pin. This is a Schmidt input.
RWC
-
55 SQOUT O Subcode Q output pin.
56 COIN I Command, data input pin from control microprocessor.
Input for both the command input acquisition clock and the
57 *CQCK I SQOUT subcode readout clock input pin.
This is Schmidt input.
Input
Reset input pin.
58 *RES I
This pin must be set low briefly after power is first applied.
59 O Test output pin. Leave open. (Notmally output a low level.)
TST11
60 16M O 16.9344MHz clock output pin.
61 4.2M O 4.2336MHz clock output pin.
Test input pin. A pull-down resistor is built in.
62 I
TEST5
Must be connected to 0V.
L output
63 VDD3V - Internal circuit 3.3V system power supply pin.
Incertitude
Test input pin.
64 I
TEST1
A pull-down resistor is built in. Must be connected to 0V.
Incertitude
Note) The same potential must be suplied to all power supply pins, i.e., VDD,VVDD,LVDD,RVDD
and XVDD.
-
- 8 -
_
EFLG
_
SBSY
_
XVSS
_
XIN
_
XOUT
_
XVDD
_
MUTER CONT8
_
RVDD
_
RCHO
_
RVSS
_
LVSS
_
LCHO
_
LVDD
_
MUTEL CONT7
_
PCCL
_
TEST4
Function description
Left channel mute output pin, General-purpose 7
output pin.
Rest to MUTEL function.
Left channel power supply pin.
Left channel output pin.
Left channel ground pin. Must be connected to 0V.
Right channel ground pin. Must be connected to 0V.
Right channel output pin.
Right channel power supply pin.
Right channel mute output pin, General-purpose 8
output pin.
Rest to MUTER function.
Output pin
to rest
-
-
H output
-
-
-
-
-
-
H output
-
-
-
Incertitude
Incertitude
Incertitude
Incertitude
-
Incertitude
Incertitude
-
Incertitude
-
-
-
L output
Clock output
Clock output
-
-
-