Ic Block Diagram & Description - Sanyo DC-DA1200M (XE-2); DC-DA1250M (SP-2) Service Manual

PARTS LIST
POWER TRANSFORMER P.W.BOARD ASSY
REF.NO. PART NO.
76 614 331 7098 ASSY,PWB,DG(Only initial)
CN451 614 017 8203 TERMINAL BOARD
CN452 614 017 8203 TERMINAL BOARD
CN455 645 005 9315 PLUG,2P
L4591 645 038 6053 INDUCTOR,181U
IC BLOCK DIAGRAM & DESCRIPTION
IC101 LC78646-UHK-E (CMOS LSI for CD Player)
SLCO
SLCIST
EFMIN
RFVDD
RFVSS
FIN1
FIN2
TIN1
TIN2
VREF
REFI
TEC
RFMON
JITTC
ADAVDD
ADAVSS
TDO
Reset
Pin
Pin Name I/O
state
No.
1 SLCO O -
Slice level
2 SLCIST AI -
control
3 EFMIN I -
4 RF AO - RF monitor pin.
5 RFVDD - - RF power supply pin.
6 RFVSS - - RF ground pin. Must be connected to 0V.
7 FIN1 AI - A+C signal input pin.
8 FIN2 AI - B+D signal input pin.
9 TIN1 AI - E signal input pin.
10 TIN2 AI F signal input pin.
11 VREF AO RFVDD/2 VREF voltage output pin.
12 REFI AI - Reference voltage seting pin.
13 FE AO ZHI FE signal monitor pin.
14 TEC AO - TE signal LPF capacitor connection pin.
15 TE AO ZHI TE signal monitor pin.
16 RFMON AO ZHI RF internal signal monitor pin.
17 JITTC A - Jitter detection capasitor connection pin.
18 ADAVDD - - Servo A/D, D/A supply pin.
19 ADAVSS - - Servo A/D, D/A ground pin. Must be connected to 0V.
20 TDO AO ADAVDD/2 Tracking control output pin. D/A output.
21 FDO AO ADAVDD/2 Focus control output pin. D/A output.
22 SPDO AO ADAVDD/2 Spindle control output pin. D/A output.
23 SPDO AO ADAVDD/2 Thread control output pin. D/A output.
24 GPDAC AO ADAVDD/2 Servo D/A general-purpose output pin.
General-purpose
25 CONT4 I/O Input mode
input / output pin 4.
General-purpose
26 CONT5 I/O Input mode
input / output pin 5.
General-purpose
27 SBCK/CONT6 I/O Input mode
input / output pin 6,
or subcode read clock input pin.
Subcode read clock input pin / FG signal input pin /
external emphasis setting pin.
28 SBCK/FG I -
Set to command pin function. Must be connected to 0V.
29 DEFECT O L Defect pin.
Rough servo / phase control automatic switching monitor
output pin.
30 V / *P O H
"H" for rough servo and "L" for phase servo.
Synchronization signal detection output pin.
Outputs a high level when the synchronization signal
detected
31 FSEQ O L
from the EFM signal and the internally generated
synchronization
signal agree.
32 MONI 1 O L Internalsignal monitor pin 1.
33 MONI 2 O L Internalsignal monitor pin 2.
34 MONI 3 O L Internalsignal monitor pin 3.
35 MONI 4 O L Internalsignal monitor pin 4.
36 MONI 5 O L Internalsignal monitor pin 5.
37 (3.3V)VSS - - Digital ground pin. Must be connected to 0V.
DESCRIPTION
1
2
3
RF 4
5
6
7
8
9
10
11
12
FE 13
14
15
TE
16
17
18
19
20
Function description
Control output.
SLCO output current adjustment resistor connection pin.
RF signal input pin.
Controlled by commands
from the microprocessor.
Any of these that are unused
must be either set up as input
pin ports and connected to 0V,
or set up as output pin ports
and left open.
TAPE MECHANISM
REF.NO. PART NO.
33 614 309 7976 ASSY,MECHA,TM-DA70TN-SH
614 312 0629 ASSY,MOTOR,FOR SERVICE
645 009 1612 PINCH ROLLER ARM ASSY
645 009 1766 RF BELT
645 033 3415 MAIN BELT
645 041 3025 R.P HEAD
645 033 8625 E HEAD 6PA
or 645 072 9775 E HEAD TC-238
Reset
Pin
I/O
Pin Name
state
No.
38 VDD - - Digital power supply pin.
39 DOUT O L Digital OUT output pin.
40 TEST I L Test input pin. Must be connected to 0V.
41 LVDD - -
L channel D/A converter
42 LCHO AO LVDD/2
43 LVSS - -
44 RVSS - -
R channel D/A converter
45 RCHO AO LVDD/2
46 RVDD - -
47 XVDD - -
48 XOUT O Oscillator Crystal oscillator
49 XIN I Oscillator
7.35kHz synchronization signal output pin.
50 FSX/16MIN I/O Input mode DF, DAC external clock input pin.
51 XVSS - - Crystal oscillator
52 C2F O H C2 flag output pin.
53 EFLG O L C1, C2 error correction monitor pin.
54 16MOUT O CLK output 16.9344MHz output pin.
55 ASLRCK I
56 ASDACK I
Antishock mode
57 ASDFIN I
58 LRSY O L
59 DATACK O L
Digital data output
60 DATA O L
61 CE I -
Micro
62 CL I -
-processor
63 DI I -
64 DO O (H) interface
65 *WRQ O H
Reset input pin.
66 *RES I -
This pin must be set low briefly after power is first applied.
67 DRF O L Focus ON detect pin.
68 VDD5V - - Microprocessor interface power supply pin.
69 VSS - - Digital ground pin. Must be connected to 0V.
70 CONT3 I/O Input mode General-purpose output pin 3. Controlled by commands from the microprocessor.
71 CONT2 I/O Input mode General-purpose output pin 2. Must be set as an input pin and connected to 0V
72 CONT1 I/O Input mode General-purpose output pin 1. or set as an output pin and left open when unused.
73 PDO1 O Phase comparison output pin 1 to control built-in VCO.
74 PDO2 O Input mode Phase comparison output pin 2 to control built-in VCO.
75 VVSS - - Built-in VCO GND pin. Must always be connected to 0V.
PLL
76 PCKIST AI - Resistor connection pin to set current for PD01 and 02 outputs.
77 VVDD - - Built-in VCO power supply pin.
78 FR AI - Resistor connection pin to set the frequency range of built-in VCO.
79 LDS AI - Laser power detection signal input pin.
80 LDD AO - Laser power detection signal output pin.
Note) The same potential must be supplied to all power supply pins, i. e. , RFVDD, VVDD, ADAVDD, VDD, LVDD,
RVDD AND XVDD. Pins operated from the microprocessor interface power supply (VDD5V) pin :
CE(61 pin), CL(62pin), DI(63 pin), DO(64 pin), *WRQ(65 pin), RES(66 pin), DRF(67 pin), CONT1(72 pin),
CONT2(71 pin), CONT3(70 pin)
- 7 -
DESCRIPTION
60 DATA
59
DATACK
58
LRSY
57
ASDFIN
56
ASDACK
55 ASLRCK
54
16MOUT
53
EFLG
52
C2F
51
XVSS
50 FSX/16MIN
49
XIN
48 XOUT
47
XVDD
46
RVDD
45 RCHO
44
RVSS
43 LVSS
42
LCHO
41
LVDD
Function description
L channel power supply pin.
L channel output pin.
L channel ground pin. Must be connected to 0V.
R channel ground pin. Must be connected to 0V.
R channel output pin.
R channel power supply pin.
Crystal oscillator power supply pin.
Connections for a 33.8688MHz or 16.9344MHz
crystal oscillator pin.
Crystal oscillator ground pin. Must be connected to 0V.
L/R clock input pin. (Must be connected to 0V when unused)
Bit clock input pin. (Must be connected to 0V when unused)
L/R channel data input pin.
(Must be connected to 0V when unused)
L/R clock output pin.
Bit clock output pin.
L/R channel data output pin.
Chip enable signal input pin.
Data transfer clock input pin.
Data input pin.
Data output pin. (Nch open drain output)
Interruption signal output pin.