TEST POINT No. & Loc.
U600-10
U601-6
U601-3
U604-3
U603-3
U603-13
J511-1,2
U502-14
U501-7
Q602,C
U608-7
U630-11
U630-12
D660-AN
U502-12
General Schematic Notes
The following table lists summary information about notes appearing in schematic diagrams.
All resistors are in ohms ±1%, 1/8W, unless otherwise specified.
1.
2.
All capacitors are in microfarads unless otherwise specified.
3.
Signal lines that are terminated by flags continue on other sheets, and may also go to other locations on the same sheet.
Example: CVPROG (SH.2 8C); "SH.2 8C" indicates the sheet number and the coordinates on that sheet where the
CVPROG signal line goes.
4.
Unterminated signal lines go to a least one other location on the same sheet.
5.
Unless otherwise noted, bias connections to integrated-circuit packages are as follows:
Table 6-3. Test Points (continued)
Signal Tested
A10 Control Board (continued)
DIVIDER CLOCK (Sheet 3)
DIVIDER RESET (Sheet 3)
ON LATCH CLOCK (Sheet 3)
ON LATCH (Sheet 3)
PWM_EN (Sheet 3)
VOS (Sheet 3)
NOTE: Temporarily move both scope leads to J511 for TP
DRV A, DRV B (Sheet 3)
OVREF (Sheets 1,3)
DP CONTROL (Sheet 3)
DP CONTROL (Sheet 3)
PREF_2 (Sheets 1,3)
DN PGM (Sheets 1,3)
DP_TST (Sheet 3)
OV COMPARATOR (Sheet 3)
Table 6-4. General Schematic Notes
14-pin packages
16-pin packages
20-pin packages
Measurement and Conditions
See Figure 6-1
See Figure 6-1
See Figure 6-1
See Figure 6-1
Held high for approximately 12 seconds at
power-on, then goes low.
+5 ± 0.2V
See Figure 6-1
+5V
+5.4V
CV Mode
Not Applicable
CV Mode
+13V
+1V
0V
0V
CV Mode
+1.5V
Common
+ 5V
pin 7
pin 14
pin 8
pin 16
pin 10
pin 20
CC Mode
-0.14V
CC Mode
0V
CC Mode
+3.25V
Diagrams 119