Abit AT7 User Manual page 50

3-20 Chapter 3
Master Priority Control:
Four options are available: Disabled ( 01 ( 10 ( 11. The default setting is Disabled. The full named
of thius item is Master Priority Rotation Control. When setting to "01", the CPU will always be granted
access after the current bus master completes, no matter how many PCI masters are requesting. With
setting to "10", if other PCI masters are requesting during the current PCI master grant, the highest
priority master will get the bus after the current master completes. But the CPU will be guaranteed to get
the bus after that master completes. With setting to "11", if other PCI masters are requesting, the highest
priority will get the bus next, then the next highest priority will get the bus, then the CPU will get the bus.
In other words, with the above settings, even if multiple PCI masters are continuously requesting the bus,
the CPU is guaranteed to get access after every master grant (01), after every other master grant (10) or
after every third master grant (11).
PCI1 Master 0 WS Write:
Two options are available: Enabled or Disabled. The default setting is Enabled. When Enabled, writes to
the PCI1 bus are executed with zero wait state (immediately) when PCI1 bus is ready to receive data. If it
is set to Disabled, the system will wait one state before data is written to the PCI1 bus.
PCI2 Master 0 WS Write:
Two options are available: Enabled or Disabled. The default setting is Enabled. When Enabled, writes to
the PCI2 bus are executed with zero wait state (immediately) when PCI2 bus is ready to receive data. If
set to Disabled, the system will wait one state before data is written to the PCI2 bus.
PCI1 Post Write:
Two options are available: Disabled or Enabled. The default setting is Enabled. When you set it to
Enabled, it can enable PCI post write buffers to minimize PCI1 master read latency.
PCI2 Post Write:
Two options are available: Disabled or Enabled. The default setting is Enabled. When you set it to
Enabled, it can enable PCI post write buffers to minimize PCI2 master read latency.
PCI Delay Transaction:
Two options are available: Disabled or Enabled. The default setting is Disabled. The chipset has an
embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support
compliance with PCI specification version 2.1.
Master Delay Transaction:
Two options are available: Disabled or Enabled. The default setting is Disabled. This item settings will
effect the system performance.
Memory Hole:
Two options are available: Disabled or 15M - 16M. The default setting is Disabled. This option is used to
free up the memory block 15M-16M. Some special peripherals need to use a memory block located
between 15M and 16M. We recommend that you disable this option.
AT7