Dram Timing Settings - JETWAY S755MAX User Manual

3-6-1 DRAM Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2003 Award Software
HyperTransport Link Width Out
HyperTransport Link Frequency
Auto Configuration
X RAS Active Time (tRAS)
X RAS Precharge Time (tRP)
X RAS to CAS Delay (tRCD)
X CAS Latency
↑ ↓ → ←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
Note: Change these settings only if you are familiar with the chipset.
RAS to CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T, 3T and 4T. (1T=1 Bus Clock)
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T, 3T and 4T.
DRAM Timing Settings
Auto
800MHz
By SPD
6 Bus Clock
3 Bus Clock
3 Bus Clock
CL =2.5
F6:Optimized Defaults
25
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