Hitachi 7K250 - Deskstar - Hard Drive Specifications page 7

7.6.2 Read DRQ interval time .................................................................50
7.7 Multi word DMA timings ........................................................................51
7.8 Ultra DMA timings ..................................................................................52
7.8.1 Initiating Read DMA ......................................................................52
7.8.2 Host Pausing Read DMA................................................................53
7.8.3 Host Terminating Read DMA.........................................................54
7.8.4 Device Terminating Read DMA.....................................................55
7.8.5 Initiating Write DMA .....................................................................56
7.8.6 Device Pausing Write DMA ...........................................................57
7.8.7 Device Terminating Write DMA ....................................................58
7.8.8 Host Terminating Write DMA........................................................59
7.9 Addressing of registers ............................................................................60
7.9.1 Cabling............................................................................................60
8.0 General................................................................................................................63
8.1 Introduction..............................................................................................63
8.2 Terminology.............................................................................................63
8.3 Deviations from standard.........................................................................63
9.0 Registers..............................................................................................................65
9.1 Register set...............................................................................................65
9.2 Alternate Status Register .........................................................................66
9.3 Command Register ..................................................................................66
9.4 Cylinder High Register ............................................................................66
9.5 Cylinder Low Register.............................................................................66
9.6 Data Register............................................................................................67
9.7 Device Control Register..........................................................................67
9.8 Drive Address Register ............................................................................68
9.9 Device/Head Register ..............................................................................68
9.10 Error Register.........................................................................................69
9.11 Features Register....................................................................................69
9.12 Sector Count Register ............................................................................69
9.13 Sector Number Register.........................................................................70
9.14 Status Register .......................................................................................70
10.0 General operation ............................................................................................73
10.1 Reset response........................................................................................73
10.2 Register initialization .............................................................................74
10.3 Diagnostic and Reset considerations .....................................................75
10.4 Sector Addressing Mode........................................................................76
10.4.1 Logical CHS addressing mode .....................................................76
10.4.2 LBA addressing mode ..................................................................76
10.5 Overlapped and queued feature .............................................................76
10.6 Power management features ..................................................................78
10.6.1 Power mode ..................................................................................78