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3. IC902 (H Driver) and IC907 (V Driver)
An H driver (IC902) and V driver (IC907) are necessary in
order to generate the clocks (vertical transfer clock, horizon-
tal transfer clock and electronic shutter clock) which driver
the CCD.
IC902 is an inverter IC which drives the horizontal CCDs (H1
and H2). In addition the XV1-XV3 signals which are output
from IC102 are the vertical transfer clocks, and the XSG1
and XSG signal which is output from IC102 is superimposed
onto XV2A and XV2B at IC907 in order to generate a ternary
pulse. In addition, the XSUB signal which is output from IC102
is used as the sweep pulse for the electronic shutter, and the
RG signal which is output from IC102 is the reset gate clock.
1A 1
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND 7
Fig. 1-3. IC902 Block Diagram
14
V
CC
13
6A
12
6Y
11
5A
10
5Y
4A
9
8
4Y
V
DD
Input
Buffer
XSHT
XV3
XSG3B
XSG3A
XV1
XSG1B
XSG1A
XV4
XV2
Fig. 1-4. IC907 Block Diagram
4. IC905 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to
Pins (26) and (27) of IC905. There are S/H blocks inside IC905
generated from the XSHP and XSHD pulses, and it is here
that CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally into
a 10-bit signal, and is then input to IC102 of the CA2 circuit
board. The gain of the AGC amplifier is controlled by the volt-
age at pin (29) which is output from IC102 of the CA2 circuit
board and smoothed by the PWM.
PBLK
PGACONT1-2
0-30 dB
PGA
CDS
CCDIN
CLP
CLPDM
DAC1
8B DAC
10B DAC
DAC2
8B DAC
INTF
3
3-W INTF ADCIN AUXIN ACLP
Fig. 1-5. IC905 Block Diagram
SHT
V3B
V
L
V3A
V1B
V
H
V1A
V4
V2
GND
CLPOB
CLP
10
ADC
DOUT
S/H
AUXCONT
0-10 dB
PGA
VRT
REF
VRB
CLP
TIMING
SHD
ADCCLK
SHP
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