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USB1
USB2
USB3
USB2.0
PCI2PCI Bridge
LPC Bridge
IDE Controller
SMBus Controller
PCIE(802.11)
CardBus Controller
1394
SD
MS
LAN
2.4 PANEL DETECTION AND INITIALIZATION
During POST, the VGA BIOS will automatically detect the LCD panel type through EDID and set
proper parameters for the LCD panel.
2.5 GPE EVENT
The GPE enable register and status register are located at offset 0x2C and 0x28 of PMIO range
respectively. The GPI0~GPI15 could be set to trigger SCI, SMI, or nothing by setting their
corresponding control bits in Dev#0/Func#0/Reg#B8h "GPI Routing Control Register" if being
selected as general purpose input.
GPE
Source
Bit
3
USB device
4
USB device
8
Ring In(PM_RI#)
11 PCI_PME#
12 USB device
13 ICH7-M internal device on bus
#0
14 USB device
24 EXTSMI#
28 KB_SCI#
Intel
0
29
1
8086h 27C9h
Intel
0
29
2
8086h 27CAh
Intel
0
29
3
8086h 27CBh
Intel
0
29
7
8086h 27CCh
Intel
0
30
0
8086h 2448h
Intel
0
31
0
8086h 27B9h
Intel
0
31
1
8086h 27DFh
Intel
0
31
3
8086h 27Dah
Intel
2
1
0
8086h 4222h
Ricoh
3
1
0
1180h 0476h
Ricoh
3
1
1
1180h 0552h
Ricoh
3
1
2
1180h 0822h
Ricoh
3
1
3
1180h 0592h
Realtek
3
7
0
11ABh 4320h
Table 2-5 GPE event table
Event
None-ACPI
ACPI
Wake Up
Wake Up
USB Controller 1
Wake Up
Wake Up
USB Controller 2
Wake Up
Wake Up
Modem ring/Cardbus ring
Wake Up /
Wake Up /
PME# of PCI device
SMI
SCI
Wake Up
Wake Up
USB Controller 3
Wake Up /
Wake Up /
PME# of internal device on bus 0
SMI
SCI
Wake Up
Wake Up
USB Controller 4
SMI
SMI
External SMI from KBC ITE8510
N/A
SCI
SCI# from KBC ITE8510
6-5
BIOS SPECIFICATION
1043h
1297h
1043h
1297h
1043h
1297h
1043h
1297h
1043h
1297h
1043h
1297h
1043h
1297h
1043h
1297h
8086h
1000h
1043h
1297h
1043h
1297h
1043h
1297h
1043h
1297h
1043h
11E5h
Description
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