Fujitsu MHC2032AT Product Manual page 18

Figure 5.5 WRITE SECTOR(S) command protocol
Figure 5.6 Protocol for the command execution without data transfer
Figure 5.7 Normal DMA data transfer
Figure 5.8 An example of generation of parallel CRC
Figure 5.9 Ultra DMA termination with pull-up or pull-down
Figure 5.10 Data transfer timing
Figure 5.11 Single word DMA data transfer timing (mode 2)
Figure 5.12 Multiword DMA data transfer timing (mode 2)
Figure 5.13 Starting of Ultra DMA data In Burst transfer
Figure 5.14 Sustained Ultra DMA data in burst
Figure 5.15 Host pausing an Ultra DMA data in burst
Figure 5.16 Device terminating an Ultra DMA data in burst
Figure 5.17 Host terminating an Ultra DMA data in burst
Figure 5.18 Initiating an Ultra DMA data out burst
Figure 5.19 Sustained Ultra DMA data out burst
Figure 5.20 Device pausing an Ultra DMA data out burst
Figure 5.21 Host terminating an Ultra DMA data out burst
Figure 5.22 Device terminating an Ultra DMA data out burst
Figure 5.23 Power on Reset Timing
Figure 6.1 Response to power-on
Figure 6.2 Response to hardware reset
Figure 6.3 Response to software reset
Figure 6.4 Response to diagnostic command
Figure 6.5 Address translation (example in CHS mode)
Figure 6.6 Address translation (example in LBA mode)
Figure 6.7 Sector slip processing
Figure 6.8 Alternate cylinder assignment
Figure 6.9 Data buffer configuration
Tables
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Table 1.5
Table 1.6
Table 1.7
C141-E050-02EN
75
5-93
Specifications (MHC2032AT/MHC2040AT)
Specifications (MHD2021AT/MHD2032AT)
Model names and product numbers
Current and power dissipation
Environmental specifications
Acoustic noise specification
Shock and vibration specification
5-73
5-76
5-90
5-96
5-99
5-100
5-102
5-103
5-104
5-105
5-108
6-3
6-4
6-5
6-6
6-8
6-9
6-12
6-13
6-14
1-4
1-5
1-6
1-7
1-8
1-8
1-9
Contents
5-
5-91
5-94
5-95
5-101
5-106
5-107
xiii