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SG H- V206 Circuit Description
7. CSP1093
CSP1093 integrates the timing and control functions for GSM 2+ mobile application with the ADC and DAC functions.
The CSP1093 interfaces to the trident, via a 16-bit parallel interface. It serves as the interface that connects a DSP to the
RF circuitry in a GSM 2+ mobile telephone. DSP can load 148 bits of burst data into CSP1093 ¡¯ s internal register, and
program CSP1093 ¡¯ s event timing and control register with the exact time to send the burst. When the timing portion of
the event timing and control register matches the internal quarter-bit counter and internal frame counter, the 148 bits in
the internal register are GMSK modulated according to GSM 2+ standards. The resulting phase information is translated
into I and Q differential output voltages that can be connected directly to an RF modulator at the TXOP and TXON pins.
The DSP is notified when the transmission is completed. For receiving baseband data, a DSP can program CSP1093 ¡¯ s
event timing and control register with the exact time to start receiving I and Q samples through TXIP and TXIN pins.
When that time is reached, the control portion of the event timing and control register will start the baseband receive
section converting I and Q sample pairs. The samples are stored in a double-buffered register until the register contains
32 sample pairs. CSP1093 then notifies the DSP which has ample time to read the information out before the next 32
sample pairs are stored. The voice band ADC converter issues an interrupt to the DSP whenever it finishes converting a
16-bit PCM word. The DSP then reads the new input sample and simultaneously loads the voice band output DAC
converter with a new PCM output word. The voice band output can be connected directly to a speaker via AOUTAN and
AOUTAP pins and be connected to a Ear-mic speaker via AOUTBN and AOUTBP pins.
8. X-TAL(13MHz)
This system uses the 13MHz TCXO, TCO-9141B, Toyocom. AFC control signal form CSP1093 controls frequency from
13MHz x-tal. It generates the clock frequency. This clock is inverted through NOT gate, TC7S04FU and is connected to
CSP1093. 13MHz clock for YMU759 uses a not-inverted clock. Clock for RF parts uses same type.
9.Camera DSP(LC99704B)
- This chipset is MCP product that combines the CCD Driver with on-chip booster circuit
and analogue/digital mixed-signal processing IC.
The booster circuit generate the supply voltages required for CCD drive.
Cameras can use either a +2.8V or +3.0V or +3.3V only power supply system.
The analogue / digital mixed-signal processing IC that integrates the signal-processing
functions required in a CCD digital camera and a rich set of addtional functions on a single
chip. Although the CDS(correlated dual sampling) and AGC circuit required for analog
processing and the clamp circuit required for A/D conversion are normally povided on
circuits, as well as an A/D converter, on a single chip.
Additionally, it also includes the pulse generator circuits required for CCD drive, the
logic circuits for the electronics iris, and the digital signal-processing circuits required to
create the digital YUV signal output. This device can take advantage of the features of
these digital signal-processing functions to provide auto white balance, automatic dropout
detection and correction, mirror image output, and a single line of memory to provide
flexibility in the external interface.
This device assumes an internal master clock frequency in the range 16 ~27 MHz.
Normally , either an external clock with that frequency is provided, or else a master clock
oscillator circuit is constructed using the built-in oscillator inverter circuit.
And this is also possible to control the CCD drive internal and enternal.
SAMSUNG Proprietary-Contents may change without notice
This Document can not be used without Samsung's authorization
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