Samsung SGH-V200 Service Manual page 9

SGH- V200 Circuit Description
9.Camera DSP(LC99704B)
- This chipset is MCP product that combines the CCD Driver with on-chip booster circuit
and analogue/digital mixed-signal processing IC.
The booster circuit generate the supply voltages required for CCD drive.
Cameras can use either a +2.8V or +3.0V or +3.3V only power supply system.
The analogue / digital mixed-signal processing IC that integrates the signal-processing
functions required in a CCD digital camera and a rich set of addtional functions on a single
chip. Although the CDS(correlated dual sampling) and AGC circuit required for analog
processing and the clamp circuit required for A/D conversion are normally povided on
circuits, as well as an A/D converter, on a single chip.
Additionally, it also includes the pulse generator circuits required for CCD drive, the
logic circuits for the electronics iris, and the digital signal-processing circuits required to
create the digital YUV signal output. This device can take advantage of the features of
these digital signal-processing functions to provide auto white balance, automatic dropout
detection and correction, mirror image output, and a single line of memory to provide
flexibility in the external interface.
This device assumes an internal master clock frequency in the range 16 ~27 MHz.
Normally , either an external clock with that frequency is provided, or else a master clock
oscillator circuit is constructed using the built-in oscillator inverter circuit.
And this is also possible to control the CCD drive internal and enternal.
10. Camera ASIC(SSH 275)
This ASIC interfaces between CCD and LCD, and this chip compresses and expands
input pictures from CCD with JPEG format.
- CCD I/F : YUV422(16 bit) format, CIF fixed size.
System clock providing CCD module (13.5 MHz) and Dot clock providing
CCD module (13.5 MHz).
- CPU I/F : Accessible to JPEG controller, a control register including, JPEG code buffer,
and a thumbnail picture buffer.
Direct access to LCD controller by switching buses.
- LCD I/F : Support LCD controller.
Accessible by switching 2 masters of the Host CPU or ASIC picture
processing .
Output format from ASIC is RGB565.
- I2C I/F : I2C master for CCD module control equipped.
CCD module is accessible from CPU wiithout paying attention to I2C, as in the
case of a normal register write/read.
- JPEG codec : YUV422 picture data is compressed to JPEG code, and JPEG code data is
expanded to YUV422 picture data.
- Clock system : As for ASIC, 27 MHz clock input from outside is the main clock.
2-divided 13.5 MHz is used as CCD module main clock output, dot clock
output to CCD module, and ASIC inner clock
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