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Port Normalization
Register
IPIR (Invert PIR)
IFLG (Invert FLG)
ICTL (Invert CTL)
ID (Invert DATA)
118 Agilent E1330B Digital I/O Module Register Information
Note
If you are using the output STRobe or PULSe handshake, you can specify
delay factors in the range 2 through 15, or you can specify 0 (no delay
period). Thus, you can specify T
and so forth for these handshakes.
If you are using the input STRobe handshake, the delay factor specified by
bits 4 through 7 is reduced by one, then multiplied by the range multiplier.
For example, the register value "00100000" for an input STRobe handshake
specifies T
On the other hand, the value "11110010" specifies T
multiplier is 10µs and the delay factor is 15 -1 =14.)
The input STRobe handshake is the only input handshake that uses a delay
period. For the other input handshakes, the value in this register has no
effect.
The Port Normalization Register allows you to normalize the port
handshake and data lines to the correct logic sense for your peripheral.
Positive true logic is the default. You can invert a line by setting the
appropriate bit equal to "1".
Port Address (0–3) base+20
7
ID
Bits 0–3
Are not used.
This bit specifies the logic sense of a peripheral interrupt request. If bit
4= "0", a rising-edge (low to high) transition of the PIR line triggers an
interrupt. If bit 4= "1", a falling-edge (high to low) transition of the PIR line
triggers an interrupt. In either case, no interrupt occurs unless peripheral
interrupts are enabled.
This bit specifies the logic sense of the FLG line.
If bit 5= "0", then positive-true logic is used: HIGH= BUSY, LOW = READY.
If bit 5= "1", then negative-true logic is used: LOW = BUSY, HIGH=READY.
This bit specifies the logic sense of the CTL line.
If bit 6= "0", then positive-true logic is used: HIGH= TRUE, LOW =FALSE.
If bit 6= "1", then negative-true logic is used: LOW = TRUE, HIGH =FALSE.
This bit specifies the logic sense of the port data lines.
If bit 7= "0", then positive-true logic is used: HIGH= TRUE, LOW =FALSE.
If bit 7= "1", then negative-true logic is used: LOW = TRUE, HIGH =FALSE.
d
= 1 ms. (The multiplier is 1 ms and the delay factor is 2-1= 1.)
d
6
5
4
ICTL
IFLG
IPIR
values from 2 to 15µs, from 20 to 150µs,
= 140 µs. (The
d
, base+21
, base+22
16
16
3
2
—
—
, base+23
16
16
1
0
—
—
Appendix B
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